The circuit is not what we would recommend but if it is working, you may not want to mess with it. You would need to "qualify" the implementation over temperature and supply variations to prove out the robustness of the solution. If you are…
The circuit is not what we would recommend but if it is working, you may not want to mess with it. You would need to "qualify" the implementation over temperature and supply variations to prove out the robustness of the solution. If you are…
Hello,
I tried to adjust the variable value and apply the clock signal at a frequency of 25 MHz, but there was no change in the output side at all.
As figure below, I have to configure in single-ended clock input mode
Looking at the forum for hints on an issue I am having with a design, I found this message:
https://ez.analog.com/message/216361?commentID=216361#comment-216361
I am troubleshooting a board where AD9707 is used and the designer supplied AVDD wit 3.3V…
我用的芯片是AD9707,该芯片的模拟电源的数字电源是分开的,现在我分别给模拟电源供电模拟3.3V,
数字电源供电数字3.3V,上电过程中发现REFIO电压有的时候很小(<200mV),这样导致最终的输出信号
幅度很小,因为此时还没有对其进行配置,默认状态下,REFIO采用的是内部参考电压,该引脚我也是按照
要求接了0.1uF的电容到地的;
测试过程中我发现,模拟电源跟数字电源的上电情况会影响该电压的大小,现在我的模拟电源比数字电源
上电提前55ms左右,这个55ms的间隔内,…
Hello, the data sheet states minimum Differential Voltage is 0.5V. Is this peak differential or peak-to-peak? In other words, may I clock the D/A directly with a LVDS driver or should I use a LVPECL or alike?
Thanks in advance.
I am developing a measurement probe , I tried to use the DAC AD9707 for converting my parallel digital 14 bit data provided by TLK 2501 transreceiver,, I configured the DAC with 3.3 V DC specification environment (AVDD= 3.3V and DVDD=2.5V)
My digital…