For anyone else, I believe the math should give 16.4k, not 1.64k
(62.5*10^-6) = 1.025/Rset
Rset = 16.4k
For anyone else, I believe the math should give 16.4k, not 1.64k
(62.5*10^-6) = 1.025/Rset
Rset = 16.4k
We are using the above part to drive a zero-IF IQ modulator that requires a DC bias of 1.15V. We have set the full scall current to 5mA (Radj = 6.4K). We have set the OTCM to 1V (from REFIO). We have a load resistance of 118 ohms. We are unable to achieve…
Hello everyone,
I'm currently working on a low power chirp generator.
Someone before me working on this, used the AD9752 (12-Bit).
I would like to replace the DAC for an AD9706 (12-bit), on the output I'd like to use an
differential to single…
We have a development card using 2 x AD9706 DACs to drive a zero-IF IQ modulator that requires a DC bias of 1.15V. We have set the full scale current to 5mA (Radj = 6.45K). We have set the OTCM to 0.5V, derived from a ADP223 Dual LDO. We have a load resistance…
Dear Mr. Deljones,
I am using the parallel input DAC (AD9706). My FPGA is giving a serial output which am converting to parallel digital inputs for the DAC using an intermediate De-Serializer. The de-serializer gives a clock output based on the frequency…
Regarding the note in the AD970x datasheet:
"The internal 1.0 V band gap reference may on occasion power up in a state that leaves the DAC output nonfunctional. To clear this state, power up again, and check that the voltage on the REFIO pin is within…
Oh. Thanks. So do you mean if I use Figure 64. The Vth could be +-1V, and the differential output Vo is always above 0V, so it could match the range of AD9238. Right? But I have another question, when I use AD9706 DAC, the output of that is above GND…
Thanks, I agreed.
BTW, please let me additional inquiry.
In a datasheet of AD9705, there is resemble sentence "The AD9704/AD9705/AD9706/AD9707 approximately 5 μs to power back up, when 3.3 V AVDD is used."
Can I suppose that the max time…