In this circuit is the reset pin connected to the correct supply. In the EVAL board this pin is connected to the analog supply. My circuit uses a AD9705 with 3.3V Analog and 2.5 Digital supply.
Hi Robert -
The AD9705 does have a one clock cycle latency. Input data is first latched, then loaded into a register that drives the DAC core. The DAC does have an inherent pipeline delay.
Looking at the forum for hints on an issue I am having with a design, I found this message:
I am troubleshooting a board where AD9707 is used and the designer supplied AVDD wit 3.3V…
Some high speed DAC have options for auto-calibration. Why and when should I use this option?