Regarding the note in the AD970x datasheet:
"The internal 1.0 V band gap reference may on occasion power up in a state that leaves the DAC output nonfunctional. To clear this state, power up again, and check that the voltage on the REFIO pin is within…
Thanks, I agreed.
BTW, please let me additional inquiry.
In a datasheet of AD9705, there is resemble sentence "The AD9704/AD9705/AD9706/AD9707 approximately 5 μs to power back up, when 3.3 V AVDD is used."
Can I suppose that the max time…
In this circuit is the reset pin connected to the correct supply. In the EVAL board this pin is connected to the analog supply. My circuit uses a AD9705 with 3.3V Analog and 2.5 Digital supply.
Looking at the forum for hints on an issue I am having with a design, I found this message:
I am troubleshooting a board where AD9707 is used and the designer supplied AVDD wit 3.3V…
Hi Robert -
The AD9705 does have a one clock cycle latency. Input data is first latched, then loaded into a register that drives the DAC core. The DAC does have an inherent pipeline delay.
Some high speed DAC have options for auto-calibration. Why and when should I use this option?