I’m using AD9705 with AVDD=3.3V, CLKVDD=3.3V and DVDD=3.3V power supply according to data sheet. The DAC_CLK and DB0~9 is controled by FPGA.

In my project, the DAC_CLK is 16Mhz, and IOUTA is connect to 400Ω resister to GND, IOUTB is connect to…

When using the AD9705 with the 1.25V internal reference what should be the voltage on the FS ADJ pin?

Hello 

is there a LTSpice Model of AD9705?

I can imagine digital part is difficult to model, but maybe analog portion model is available?

We are trying to use another DAC to adjust the voltage across RSET to allow for adjusting the Full Scale Current Output. Has anyone done this before? Is this possible?

Hello All,

I am confusing on the figure 89 of AD9705 Data Sheet.

Based on the specification section, the output compliance voltage range is +/- 0.8V, from OTCM to IOUTA/IOUTB.

In the figure, the OTCM terminal is tied to GND, which means the IOUTA…

Hi,

I'm currently using the AD9705 in conjunction with the ADA4430-1 for a video design project. The design works. However, After a few months of field trial , several units came back without video. I measured all the signals going into the DAC and they…

问题1：AD9705在只使用单端时钟时，14引脚CLKCOM是否需要接地，数据手册中只说明单端时钟应用时需要将15引脚和14引脚连接；

问题2：请帮忙查看一下在PIN模式下外围电路是否有错误。

Hello!

I want used DAC AD9705 in single-ended mode with 499 Ohm load resistor for voltage range from 0 to 1 V. I have two question. Where connect the OTCM output pin in this mode? What is the minimum update frequency in this mode?

Best regards.

I'm adapting a design from a retired engineer with two discrete AD9705s being used for IQ modulation. I noticed that in an earlier design, he had used a single AD9763. Comparing both of these options, it seems that the two discrete AD9705s beat the AD9763…