• RE: AD9705 DAC Failure

    Hi -

    What is the voltage on the REFIO pin of the AD9705 on a failed board? What Are the supply voltages you are using on the AD9705?


  • RE: Max time to power back from sleep mode of AD9740

    Thanks, I agreed.

    BTW, please let me additional inquiry.

    In a datasheet of AD9705, there is resemble sentence "The AD9704/AD9705/AD9706/AD9707 approximately 5 μs to power back up, when 3.3 V AVDD is used."

    Can I suppose that the max time…

  • Spice Model of AD9705 or Anoalog Portion


    is there a LTSpice Model of AD9705?

    I can imagine digital part is difficult to model, but maybe analog portion model is available?

  • AD9705 FS ADJ

    When using the AD9705 with the 1.25V internal reference what should be the voltage on the FS ADJ pin?

  • RE: AD9705 with current mirror load

    Hi Robert -

    The attached scope capture shows normal behavior of the AD9705 driving a resistor.

    The rising edge of your pulse appears to be five 100ns samples. The settling time behavior looks good from my perspective. It's consistent with the 11ns…

  • AD9705 FS ADJ with dac

    We are trying to use another DAC to adjust the voltage across RSET to allow for adjusting the Full Scale Current Output. Has anyone done this before? Is this possible?

  • AD9705 in single-ended mode


    I want used DAC AD9705 in single-ended mode with 499 Ohm load resistor for voltage range from 0 to 1 V. I have two question. Where connect the OTCM output pin in this mode? What is the minimum update frequency in this mode?

    Best regards.

  • AD9705数模转换器外围电路问题,请协助解决。



  • RE: AD 9707 Power Supply

    In this circuit is the reset pin connected to the correct supply. In the EVAL board this pin is connected to the analog supply. My circuit uses a AD9705 with 3.3V Analog and 2.5 Digital supply.

  • RE: AD970x Clock Latency

    Hi Robert -

    The AD9705 does have a one clock cycle latency. Input data is first latched, then loaded into a register that drives the DAC core. The DAC does have an inherent pipeline delay.