• AD9695 ADC Clock Rates

    I want to run AD9695 at three ADC Clock rates, 320M, 400M and 480M. I will decimate by 8/10/12 to maintain a constant output rate. I am working with the ADS7-V2EBL=Rev C eval PWB and the AD9695-1300 EBZ.

    ADC Clock is applied to P202 of ADC Eval PWB; Ref…

  • AD9695 Clock Status Register

    Hi there,

    I'm working on bringing up an AD9695 and I'm having some issues with the clock status register. The data sheet for the AD9695 is rather vague in regard to this bit - is it some PLL locking bit? I've probed the chip pin(s) and we see…

  • AD9695 PLL not locked


    I am working on AD9695. After configuring the JESD interface and enabling the link via control link register (0x571), i consult the PLL lock status register (0x56F) and it returns 0 which means that PLL is not locked. 

    my input clock is 1.2Ghz and…

  • AD9695 noise density

    The AD9695 has 3 input ranges - 1.36V/1.59V/2.04 Vpk-pk, with corresponding  changes in noise density.  Can the Virtual Beta tool simulate these changes - it appears not.

    With Virtual Beta, the noise density is -149.5dBFS, considerably worse than the …

  • AD9695 ACE Plugin


    I am trying to install the ACE plugin for the AD9695 but I am getting an "Unapproved" error on the plugin (see screenshot) and it does not appear as an available plugin. How can I fix this?

    Thank you

  • AD9695 FMC Card Reference Design

    Hi, I opened an example project of the AD9695 according to the HDL guide and the project has no block diagram. 

    What could be the problem?

     The link with the project: (https://github.com/sarpadi/hdl/tree/dev_ad9695/projects/ad9695_fmc/zcu102


  • AD9695 lane mapping

    Is it possible to map all four lanes in the AD9695 to a single ADC in full BW mode? With a clock of 1300MHz, we would like to use all 4 lanes at a rate of 6.5Gbps from a single ADC, not using the other ADC.

  • RE: AD9695 x2 decimation

    you can setup the AD9695 as you have mentioned. there is an example setup in the datasheet albeit it has slightly different setup. but it provides a general outline. 

    Do I need to program coefficients for the filters ?

    not if you are using…

  • AD9695 DC power

    For the dual ADC AD9695-625, is it possible to shut down one of the ADCs to save current. We have independent RF inputs to A & B ADC cores.

    We are using a DDC/NCO to decimate from 400M to < 50M.  From data sheet, I expect the DC power is approx…

  • AD9695 Power On Sequence Requirement


    I am using AD9695 ADC chip in my design.

    Following Power Supplies are used here

    1. +0.95V for AVDD1, AVDD1_SR, DVDD and DRVDD1

    2. +1.8V for AVDD2, DRVDD2 and SPIVDD

    3. +2.5V for AVDD3

    Please provide the Power On Sequence Requirement for that chip…