• RE: AD9695 input circuitry

    perhaps this could explain the loss : Who Ate My dBs? | Analog Devices

    the s-parameters are measured directly at the input pins (VIN+/VIN-) of the ADC. it represents the input return loss of the ADC inputs. the datasheet has the plot. 



    I'm driving sysref to AD9695 from HMC7044.

    Since I use 1shot sysref it must be DC coupled. HMC can't work in LVDS mode for DC coupled 1shot sysref (known issue) thus forces me to work in LVPECL.

    from HMC (driver) point of view, recommended…

  • RE: AD9695 link activation error

    FPGA ref clk and input clock to ADC from different sources,

    you mean different hardware equipment?   These clocks must have a  common source. 


  • RE: AD9695 FMC Card Reference Design

    Hi Andrei,

    It worked! Thank you very much!


  • AD9695


  • RE: AD9695


    The AD9695 has a differential input with a 1.41V common mode voltage and a 1.59Vp-p input range. This means that Vin+ and Vin- may have signal swing of 1.41V +/-0.795Vp-p. May I know what do you mean by small DC signals?

    Figure 70 of the datasheet…

  • AD9695 Evaluation

    I'm  planning to evaluate the AD9695 ADC using the EVAL-AD9695 board. It looks as though I can use either the ADS7-V2EBZ or ADS8-V1EBZ as a motherboard for this. Is there a recommendation on which one to use? 


  • AD9695 question

    I want to use ADS7-V2EBZ as data capture for board level test and also Xilinx Development Tool for JESD204B interface between AD9695-625 ADC chip and Xilinx FPGA.

    If we purchase the ASD7-V2EBZ, can we get the source Verilog code of Xilinx chip?

  • RE: AD9695 x2 decimation

    you can setup the AD9695 as you have mentioned. there is an example setup in the datasheet albeit it has slightly different setup. but it provides a general outline. 

    Do I need to program coefficients for the filters ?

    not if you are using…