My customer has purchased the AD9695-1300EBZ and ADS8-V1EBZ and would like to test them.
1. Could you please provide the user guide for AD9695 EVB that works with ADS8-V1EBZ ?
I could only find the user guide for AD9695 EVB that works with ADS7…
My customer has a few questions about AD9695.
1. What is the start-up sequence for AD9695 ?
2. Is there a way to save the AD9695 register values that user set up in offline mode ACE ?
The FPGA on the ADS7-V2EBZ supports a max lane rate of 12.5Gbps. This limits its capability to simultaneously process both AD9695 channels operating at max lane rate. The ADS7-V2EBZ can support a single AD9695 channel operating at full rate…
Our standard AD9695 Customer evaluation brd uses the FMC connector and mates to our ADS7-V2EBZ Virtex7-based capture hardware described here: http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL…
EVALUATING THE AD9208 / AD9689 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki] step 8.
the same steps should apply to AD9695. For more information please see AD9695 datasheet.
I want to use ADS7-V2EBZ as data capture for board level test and also Xilinx Development Tool for JESD204B interface between AD9695-625 ADC chip and Xilinx FPGA.
If we purchase the ASD7-V2EBZ, can we get the source Verilog code of Xilinx chip?
My customer intends to use the AD9695-1300 with the following configurations.
- Clk in : 983.04MHz
- L=4, M=4, DDC Decimation = 2
- JESD lane rate = 9830.4 MHz/ lane
Is the configuration availalbe on the AD9695-1300 ?
With one channel off, you would be around 60% of total power. You can check out the AD9697 for comparison. This is the single channel version of the AD9695.
You can refer to the memory map registers 0x0008 and 0x0002 to disable/power down one channel…
We currently use the AD9680 dual-ADC at 1000 MSa/sec, L=4, M=2, F=1, N'=16.
I am observing amplitude drop of around 0.3dB at input frequencies below 5MHz. The amplitude drop is abrupt enough to make if unfeasible for compensation using input filters. What can be the reason for this? Can it be mitigated?It looks like low…