• Question about ad9694

    I want to disable FACI function. I write data 0x56 into register 0x0571. But 0xfc has always been inserted into the data stream. 

    This is no effect at all.

    How can I disable FACI in ad9694


  • AD9694 Register setting


    Are there any sample settings of the registers or documents about sending order of the registers? I received the question about that from customer. He would like to know how to send the registers from power-on to normal operation of AD9694.


  • RE: ADS7-V2EBZ (AD9694) SMA GPIO J6 output signal

    J6 ready signal is used when the ADS7 is setup in a trigger mode

  • AD9694 disparity errors

    Good Morning  

    I have developed a design that use the Xilinx FPGA ultrascale “XCKU040-FFVA1156” that interface the ADC (AD9694) by using 4 lines JESD.

    The JESD line rate is > 4 Gbps.

    The FPGA design is implemented using VIVADO 2018.1 and the Xilinx…

  • AD9694 register scope

    Hi -

    The data sheet for the AD9694 states that register names are prefixed with either global map, channel map, JESD204B map, or pair map.
    There are a few that do not follow this convention.  Can someone please confirm the scope of each of these registers…

  • AD9694 Sync / CGS Problem

    Our application uses an AD9694 in full bandwidth mode, utilizing 4 ADC cores, 4 lanes, 12Gb/s lane rate, and JESD204B subclass 1.  Sample Clock is 600MHz.  

    We have an AD9694 device that seems to not interpret the SYNCINB_CD input correctly.  We are driving…

  • AD9694 EBZ-500 schematic


    I'd like to ask how can I download the schematic of AD9694 EBZ-500. The link to design files doesn't work. I need to connect this board to Xilinx ML605 board (FMC wiring).



  • AD9694-Channels not synchronous

    Hi, I am evaluating AD9694-500EBZ with the ADS7-V2EBZ FPGA data capture board. I expect the ADC captures all channels synchronously. I split a sine wave signal and fed the signal to any two of the four channels. However, the data captured in VisualAnalog is…

  • AD9694 SYSREF to CLK timing

    The datasheet for the AD9694 specifies a -44.8ps setup time and a 64.4ps hold time for the SYSREF signal with respect to the CLK edge. There is also the following timing diagram:

    This shows the setup and hold timing conventions that I am used to: SYSREF…

  • Vivado Project files for ad9694-500ebz?

    On the page for the ad9694-500ebz (https://wiki.analog.com/resources/eval/ad9694-500ebz), I see this:


    Is the Vivado project that generated this file available?