• AD9694 Full Bandwidth Mode operation.

    Dear Experts,

    My customer wants to ask you about the following questions related to "Full Bandwidth Mode" in AD9694. Could you please reply to the following questions?

    [Customer's AD9694 usage]:
    1) Sampling rate: 250[Msps].
    2) ADC channels:…



    The crosstalk is dependent on a myriad of factors that are external to the AD9694. I would use the datasheet as the best case guide for crosstalk. There is a possibility that the crosstalk could degrade by a few dB at higher frequency but we have…

  • AD9694 Sync / CGS Problem

    Our application uses an AD9694 in full bandwidth mode, utilizing 4 ADC cores, 4 lanes, 12Gb/s lane rate, and JESD204B subclass 1.  Sample Clock is 600MHz.  

    We have an AD9694 device that seems to not interpret the SYNCINB_CD input correctly.  We are driving…

  • AD9694 configuration

    I'm using AD9694 ADCs running at 400MHz connected to a Kintex 7.  I've found that every 30th time or so that the ADCs are configured, one or all four channels have corrupted data.  I believe I've corrected the problem by adding 5ms delays between…

  • AD9694 Settling

    Hi, I'm running an AD9694 at 400MHz.  I'm testing the settling time with a flat top input.  I see behavior as shown in the attached images - the input to the AD9694 is flat, but the digitized output shows an overshoot and slow settling over a few…

  • RE: Can AD9694 support the simple 500[Msps] 14-bit Quad ADC operations with disabling any filtering function built-in AD9694?

    Hello Judy-san,

    Thank you so much for your kind reply.

    I am so sorry to ask you again and again. Let me ask you the following question again.

    Q1-2: You told us about the following feedback:
    "The AD9694 by default does not enable any DDCs, and hence…

  • Channel-to-channel consistency of AD9694


    what is the performance of aperture delay matching between quad channels of the same chip of AD9694? 

    Best regards,


  • RE: AD9694 do not start convertion


    What are you seeing at the output of the AD9694 when the "the conversion does not start"?


  • RE: AD9694 Losing Sync & Real Data Output Only?

    I'm still having this issue; has anyone working with the AD9694 (or any JESD data converter) seen something similar? 

  • AD9694-500EBZ, 1GHz clock source compatibility with LVPECL, LVDS, or LVCMOS output termination

    Hi There,

    I am wondering if AD9694-500EBZ, 1GHz clock source port (J203) and ADS7-V2BZ, J3 port are compatible with the LVPECL, LVDS, or LVCMOS output termination signal type.  Could you please let me know if any of the above output termination types are…