• AD9694 configuration

    I'm using AD9694 ADCs running at 400MHz connected to a Kintex 7.  I've found that every 30th time or so that the ADCs are configured, one or all four channels have corrupted data.  I believe I've corrected the problem by adding 5ms delays between…

  • AD9694 Settling

    Hi, I'm running an AD9694 at 400MHz.  I'm testing the settling time with a flat top input.  I see behavior as shown in the attached images - the input to the AD9694 is flat, but the digitized output shows an overshoot and slow settling over a few…

  • AD9694 vs AD9695 DDC/NCOs

    When using the DDC/NCO, can the AD9694 ADC operate in the 2nd Nyquist zone in the same way for the AD9695?

    I have tested the AD9595 eval PWB; Clock Input is 400M, and decimation rate =8, digital output is 50M bandwidth, centered around the NCO freq selected…

  • RE: AD9694 Losing Sync & Real Data Output Only?

    I'm still having this issue; has anyone working with the AD9694 (or any JESD data converter) seen something similar? 

  • RE: AD9694 disparity errors


    The AD9694 will not be sending characters that cause disparity errors. But what can happen is that the characters get corrupted during their transmission to the FPGA. If noise or other distortions couple into the high speed lane this can affect the…

  • RE: AD9694 wake-up time from power down mode

    Hi Akira,

    For the AD9694:

    Wake up time from standby is 3ms.

    Wake up time from power down is 10ms.


  • Where do I find the schematic for the AD9694-500EBZ?

    The link from the page "EVALUATING THE AD9694 QUAD CHANNEL 500 MSPS ADC" does not work (looks like the documents have not been uploaded to the FTP server). I need the schematic to plan how to integrate the board into my evaluation platform.

  • RE: AD9694-EBZ board reset error

    Thank you for correcting me. I am sorry for providing the wrong information. I wrongly assumed the AD9694 ACE plugin had the analysis portion built in to it like the AD9208. 

  • AD9694 EBZ-500 schematic


    I'd like to ask how can I download the schematic of AD9694 EBZ-500. The link to design files doesn't work. I need to connect this board to Xilinx ML605 board (FMC wiring).



  • RE: ad9694 input clock



    The clock detection threshold needs to be adjusted in order to run the AD9694 at 240MSPS. You can use register 0x011A to adjust the threshold. Please refer to the datasheet fore more details.