Thank you so much for your kind reply.
I am so sorry to ask you again and again. Let me ask you the following question again.
Q1-2: You told us about the following feedback:"The AD9694 by default does not enable any DDCs, and hence…
What are you seeing at the output of the AD9694 when the "the conversion does not start"?
I'm still having this issue; has anyone working with the AD9694 (or any JESD data converter) seen something similar?
I have a system design with two AD9694s, and I have difficulty is synchronising the two ICs.
Each quad AD9694 is set up as 4ch DDCs, sampling at 400MHz, input clock at 1600MHz. An LTC6951 provides the clocks and the Sysrefs to the ADCs and an Arria V…
The data sheet for the AD9694 states that register names are prefixed with either global map, channel map, JESD204B map, or pair map.There are a few that do not follow this convention. Can someone please confirm the scope of each of these registers…
The link from the page "EVALUATING THE AD9694 QUAD CHANNEL 500 MSPS ADC" does not work (looks like the documents have not been uploaded to the FTP server). I need the schematic to plan how to integrate the board into my evaluation platform.
The AD9694 will not be sending characters that cause disparity errors. But what can happen is that the characters get corrupted during their transmission to the FPGA. If noise or other distortions couple into the high speed lane this can affect the…
When using the DDC/NCO, can the AD9694 ADC operate in the 2nd Nyquist zone in the same way for the AD9695?
I have tested the AD9595 eval PWB; Clock Input is 400M, and decimation rate =8, digital output is 50M bandwidth, centered around the NCO freq selected…
For the AD9694:
Wake up time from standby is 3ms.
Wake up time from power down is 10ms.
the input buffer of AD9694 provides a 200 ohm differential termination impedance according to the data sheet (left figure below). Both the suggested input matching networks (p. 24 in the datasheet, right figure below) thus present an approximate