• AD9694 EVAL AVDD1

    I have designed an ADC board based on the AD9694.

    For the power approx 1V power rails (AVDD1, DVDD, DRVDD1) I followed the AD9694 evaluation board design and used an ADP1762 with the voltage adjust resistor = 6k34 and the same two stage filter circuit…

  • AD9694 IBIS-AMI model

    Does Analog provide a IBIS-AMI model for the AD9694?  If not is there another model I can use to simulate the JESD204 serdes link? 

    Searching through EZ it looks like the AD9680 may do the job and my HyperLynx sim with this model shows promising results…

  • On the use of ad9694

    hi

    In order to better use ad9694, a small demo board was made according to ad9694-500ebz. But the bottom noise of the board was about-98dbc (without analog clock and empty mining). In the same case, the bottom noise of ADI ad9694-500ebz board was about…

  • On the use of ad9694

    hi

    In order to better understand the use of ad9694, a small demo board is made according to ad9694-500ebz, but the bottom noise of the board data collection is about - 98dbc (without analog clock, air mining). In the same case, the bottom noise of air…

  • AD9694-500ebz, ADS7-v2EBZ, visual analog and ACE issues

    Hi support.

    on behalf of a client.

    using this set up as advise by the part AD9694-500ebz, ADS7-v2EBZ, visual analog and ACE.

    question “In the ACE application, in register view window, they don’t see register 0x011A. they would like to amend it to see if…

  • RefClk input from AD9694-500EBZ

    Hello,

    We are currently using the data capture board ADS7v2 connected to AD9694-500EBZ (new version) for some tests. According to ADI's wiki page, the RefClk is connected into J3 of ADS7 card. And followed by that, we can successfully obtain the data…

  • 关于AD9694使用问题

    为了更好的摸底使用AD9694，根据AD9694-500ebz制作了一个小DEMO板，但是自己做的这个板子数据采集回来底噪在-98dbc左右（不加模拟时钟，空采），同样情况下我用ADI的AD9694-500ebz板空采的底噪在-115dbc左右。检查了电源电压跟AD9694-500ebz的电压一致（电源噪声也在50mv左右），请问这种情况下是什么原因造成了自己做的板子AD9694底噪这么高？

  • 询问AD9694的Input Common Mode设置问题

    我正在使用AD9694设计一款无线电设备。Datasheet中关于Input Common Mode的介绍我没有理解。我的问题是：

    1. AC耦合输入，需要配置那些寄存器？如何配置？
    2. 寄存器0x18E0、0x18E1、0x18E2如何配置？各Bit有何含义?
    3. 寄存器0x18E3 Bit6 所指的External VCM Buffer的使能是指输出VCM电压到管脚？如果我配置为AC耦合，这一位如何配置？
    4. Datasheet图57中的VCM Buffer就是Datasheet中所指的External VCM…

  • AD9694: Input Common Mode

    I did not understand the introduction of Input Common Mode in the Datasheet.

    My question is:

    AC coupling input, which registers need to be configured? How to configure it?

    How to configure the registers 0x18E0, 0x18E1, 0x18E2? What is the meaning of each…

  • Starting point to get Eval board AD9694-500EBZ working with Xilinx Virtex-7 FPGA VC709 Connectivity Kit

    Hi team.

    I would like to use AD9694 in the project, and I checked the measurement setup in the user guide (with ADS7-V2EBZ). I understand its an evaluation board which intended to be used to test the ADC, not for development. But I still wonder how flexible…