On the page for the ad9694-500ebz (https://wiki.analog.com/resources/eval/ad9694-500ebz), I see this:

ad9694_ads7v2.bin

Is the Vivado project that generated this file available?

Good morning,

we are using the Analog Devices evaluation board 1.3.2470.0 to test the AD9694.

It is possible to dump the configuration of the AD9694 by readback the register memory map ?

Thanks, Best Regards

mauriziob

Hello,

what is the performance of aperture delay matching between quad channels of the same chip of AD9694? 

Best regards,

Lin

I'm trying to understand the AD9694 - according to the datasheet, "By default, the AD9694 is configured to use four converters and four lanes."

However, it looks like that is *total* number of lanes, and that the device actually uses 2…

Hi,

Currently I try to connect the AD9694-500EBZ to the ZCU102 Zync Ultrascale evaluation kit. On the FPGA reference design page I see some user guides for different FMC-boards that provide a good starting point but unfortunately the AD9694-500EBZ board…

In datasheet on AD9694 (Page 7), the value of CROSSTALK is indicated only for the frequency of 155 MHz. Are there data from CROSSTALK on other frequences? I'm interested in the range 250-500 MHz.

I'm using AD9694 ADCs running at 400MHz connected to a Kintex 7.  I've found that every 30th time or so that the ADCs are configured, one or all four channels have corrupted data.  I believe I've corrected the problem by adding 5ms delays between…

Hi, I'm running an AD9694 at 400MHz.  I'm testing the settling time with a flat top input.  I see behavior as shown in the attached images - the input to the AD9694 is flat, but the digitized output shows an overshoot and slow settling over a few…

Dear Experts,

My customer wants to ask you about the following questions related to "Full Bandwidth Mode" in AD9694. Could you please reply to the following questions?

[Customer's AD9694 usage]:
1) Sampling rate: 250[Msps].
2) ADC channels:…