• AD9689 SFDR issue


    We are using AD9689-2000 in a custom designed board. We have SFDR issue in some frequencies. The spurs that limits the SFDR to 60 dBFs are 2nd and 3rd harmonics.

    We tested the ADC with both 1600 MSPS and 1350 MSPS . The clock is produced and provided…

  • ad9689 sample rate in 2.7GHz can't work

    AD9689-2600 data sheet promise max 2.7G sample rate,I use in 2.6G full bandwidth mode work well,but in 2.7G the PLL can't lock.Anyone can help with this problem? Thanks!

  • AD9689 with JESD in FPGA


    While Testing AD9689 with FPGA , link is not stable . after some time link going down with data as zeros (sync and rx_tvalid going low) and sync with narrow pulses. we are suspecting that its ILAS issue ,but we verified the clocks and parameters…

  • AD9689 with JESD204B


    I am trying to capture adc data from ad9689 in Kintex ultrascale fpga. I used same register setting given in a datasheet for full bandwidth mode and sequence too.I can able to read back pll status and sampling clock detection registers .test pattern…

  • AD9689 Data Rearrangement


    I was trying to capture the data from ad9689 eval board by feeding 100 Mhz , getting some data but I am unable to re arrange and plot it .

    I am getting 256 bits of data from ad9689 eval board (M=2,L=8,F=1,s=2) with full band width mode,which is given…

  • AD9689 Digital output


    I want to get data from ad9689, which is similar to page 82 of the manual. I use DDC to output IQ data.

    Different from the example Lane = 2, I use fs=2400M, DCM=8, lane = 8.

    I don't know the order of the output data, and I can't find…

  • AD9689 maximum input voltage

    I have a question related to the maximum input signal of AD9689. The question is somehow similar to https://ez.analog.com/data_converters/high-speed_adcs/w/documents/2708/ad6645-max-input-signal and ez.analog.com/.../381667

    In my application, I have signals…

  • AD9689 input range

    According to the  reference design, we placed a bal-006 in front of the ADC input, so that the amplitude of the ADC sampling signal is indeed reduced by about 6dB. My input signal is actually a 1G analog single ended signal. What should I do to ensure…



    I am looking the schematics, but I don't find where do the EXT_REFCLK_TO_FPGA signals come from?

    We need them because those connections to FPGA are the only ones connected to GT clock buffers...

  • RE: AD9689 Signal Monitor Register bitmapping

    It turns out that this is as simple as taking the upper 13 bits of the 20 bit value.

    Unclear why this wasn't immediately apparent before, perhaps due to a misconfiguration of the signal monitor regsiters.