• AD9689 Data Rearrangement


    I was trying to capture the data from ad9689 eval board by feeding 100 Mhz , getting some data but I am unable to re arrange and plot it .

    I am getting 256 bits of data from ad9689 eval board (M=2,L=8,F=1,s=2) with full band width mode,which is given…

  • AD9689 Digital output


    I want to get data from ad9689, which is similar to page 82 of the manual. I use DDC to output IQ data.

    Different from the example Lane = 2, I use fs=2400M, DCM=8, lane = 8.

    I don't know the order of the output data, and I can't find…

  • AD9689 input range

    According to the  reference design, we placed a bal-006 in front of the ADC input, so that the amplitude of the ADC sampling signal is indeed reduced by about 6dB. My input signal is actually a 1G analog single ended signal. What should I do to ensure…



    I am looking the schematics, but I don't find where do the EXT_REFCLK_TO_FPGA signals come from?

    We need them because those connections to FPGA are the only ones connected to GT clock buffers...

  • AD9689 maximum input voltage

    I have a question related to the maximum input signal of AD9689. The question is somehow similar to https://ez.analog.com/data_converters/high-speed_adcs/w/documents/2708/ad6645-max-input-signal and ez.analog.com/.../381667

    In my application, I have signals…

  • RE: AD9689 Signal Monitor Register bitmapping

    It turns out that this is as simple as taking the upper 13 bits of the 20 bit value.

    Unclear why this wasn't immediately apparent before, perhaps due to a misconfiguration of the signal monitor regsiters.

  • AD9689: Settling time of SERDES output


    I have a question about the settling time of AD9689.
    Our customer wants to know when he should release the reset state of the FPGA.
    The FPGA should be wait to release the reset state until settled the SERDES output of AD9689 to start the CDR of the…

  • AD9689 - 2600EBZ Configuration

    Hi I am using AD9689 - 2600EBZ with ZCU106 board I am able to configure the ADC via SPI.
    Following is the configuration I have used as given on page 81 in the datasheet.
    • Two 14-bit converters at 2.56 GSPS.
    • Full bandwidth application layer mode…

  • ad9689 balun transformer


    The balun used in Eval board is BAL0006SM. Can you suggest an alternate part for this?  

  • RE: AD9689 CAN'T WORK

    Hi chennash30, even I am facing same issues now ,I hope you found the solution for this,please let me know