• Questions about the AD9684 LVDS output

    My customer is using only one of AD9684's 2 ADCs, and I am trying to receive the received input as 2 DDCs. (Two carrier signals)

    The two DDCs will only be used in real.

    At this time, when using only real (I data) two DDC outputs, please inform us…

  • AD9684: Mapping 4x real and complex channel voltage outputs for axi-ad9684-core-lpc

    I've currently implemented an AD9684 HDL hardware design and iio-oscilloscope shows the following two channels:

    Here is my ad9684-fmc.dtsi:

    /*
     * Analog Devices AD9684 FMC evaluation board.
     */
    / {
    	clocks {
    		ad9528_clk_out_0: clock@0 {
    	…

  • AD9684 PCB design guidelines

    Hi

    Please provide PCB design guidelines for AD9684 along with PCB stack up, Impedance, Thermal guidelines.

    Thank you

    mahi

  • RE: The AD9684 is a 500 MSPS ADC.Why the sampling rate of the AD9684 is 1Gsps?

    Hi,

    The max sampling rate of the AD9684 parallel LVDS output model is indeed 500MSPS. Table 16 in the AD9684 rev0 datasheet inadvertently reflects the DDC Filter capabilities of the JESD204B output enabled model which does support a sampling rate of…

  • RE: Input Gain profile(curve) of AD9684

    , the gain flatness can change a lot depending on the package and the front end components. We do not have a gain flatness curve for AD9684, but the AD9684 derives the cores from AD9680. 

  • AD9684 dtsi

    I've created an AD9684-FMC-500EBZ hardware design for the ZC706 evaluation board, based on the DAQ1 design, using HDL 2019_r1 branch.

    I've created and built the linux kernel and rootfs using petalinux-2019.2 workflow.

    However, when I boot the…

  • AD9684 Input termination

    What is the use for the variable input termination in AD9684? What are the
    options available?

     

    The AD9684 has programmable input terminations. This termination can be
    programmed using
    SPI register 0x016. Available options are 400Ù…
  • AD9684 MULTICHIP SYNCHRONIZATION

    Hi

    I have 2 AD9684 and I need to synchronize both for data output acquisition with a FPGA. I'd like to use one DCO (500 MSPS) for both AD9684 for data capturing, so I need both DCO are perfectly in phase.

    Both AD9684 clock input are at same 500 MHz…

  • AD9684 MULTICHIP SYNCHRONIZATION

    Hi

    I have 2 AD9684 and I need to synchronize both for data output acquisition with a FPGA. I'd like to use one DCO (500 MSPS) for both AD9684 for data capturing, so I need both DCO are perfectly in phase.

    Both AD9684 clock input are at same 500 MHz…

  • AD9684 Noise density


    In the datasheet of AD9684 , the noise density is disclosed -155 dBFS/Hz at 500 MSPS.

    Is this number including 8 times aliased noise floor within 2 GHz bandwidth?