• AD9680:User pattern sent from AD9680 not matching when checked at FPGA Rx side.

    Hi team

    I am sending user patterns from AD9680 by setting reg 0x550 to value 8. This is full bandwidth mode with reg 0x570=89.

    ADC rate=625 Mhz

    Data rate =6.25 Gbps

    Below are the registers related to user patterns set:

    0x551   8C

    0x552   8E

    0x553   7C


  • RE: ad9680 spi2.1: AD9680 PLL UNLOCKED

    Hi All,

    I've cherry-picked the following commits into our 2019_R2 branch (https://github.com/PrecisionWave/linux/tree/2019_R2_PCW) to get the ad9680 working with the ad9208 driver:

    32af9cfdac0e iio: adc: ad9208: IIO_CHAN_INFO_SAMP_FREQ use chip de…

  • AD9680 (using ad9680-1000ebz) clock-divider phase

    Hi EZ,

    I am evaluating AD9680. I connect the same signal to both Channels, I sample at 1GSPS and the data comes spot on the same.

    However no matter what I select in 0x10C the data from ADC ChA vs ChB is never shifted by any clock delay. 

    I've tried 1 GHz…

  • AD9680 JESD data out array?


    I'm using AD9680-820 with development board.

    1) LMFS=4112(REG x570 = x80). JESD output has 128bits data.

    I made data format with 'JESD204_FrameMapping_SingleMode.exe' program. 

    How can i match data from 128bits data(JESD RX core output…

  • AD9680 fails after re-configuring data-link

    We are using AD9680 for data acquisition in our project. The design was modified from FMCDAQ2, which uses AD9523-1 as clocking source for JESD204 datalink. The difference is, we only have one analog channel, and the sample rate is 1 GSPS. 

    We configure…

  • AD9680: PRBS 23 issue and queries

    Hi team

    I am using AD-FMCDAQ module and looking to test the interoperability of AD9680 device with our FPGA. Since the analog sine waveform received on the FPGA side is having some spikes and dips hence, I am looking to perform PRBS check for bit error…

  • RE: HMC7043 and AD9680 configuration

    I have the same problem, the sync signal is pulled low periodically, have you solved this problem?

  • AD9680: How samples from ADC are split across lanes?

    I have gone through AD9680 datasheet and as per my understanding samples from each ADC converters are split across two lanes. Since AD9680 has two ADC converters say A and B. So samples from ADC 'A' will split across lane 0 and lane1 such as sample 1…

  • RE: AD9680 (AD9680-500EBZ) and Aria 10 SoC interface

    Hi Umesh, 

    I guess there is no chance that AD will release the HDL for the interface and JESD204B decoder to increase the speed of implementation on an Altera/Intel platform? If there was, that would be a very valuable help.