• AD9680:User pattern sent from AD9680 not matching when checked at FPGA Rx side.

    Hi team

    I am sending user patterns from AD9680 by setting reg 0x550 to value 8. This is full bandwidth mode with reg 0x570=89.

    ADC rate=625 Mhz

    Data rate =6.25 Gbps

    Below are the registers related to user patterns set:

    0x551   8C

    0x552   8E

    0x553   7C

    0x55…

  • AD9680 PLL not locked

    Hi. I am using AD9680-1000. A clock generator is used to provide sampling clock for AD9680.

    When the sampling clock is 1GHz or 400MHz, AD9680 works well. But when the sampling clock is 500MHz, the bit7 of the 0x56F reg is 0 (PLL not locked). The 0x11C…

  • about AD9680 output data

    I try to capture signal data by  AD9680-LF500EBZ+ADS7-V2.

    The sample rate be set as 500 MHz and use the VisualAnalog's "Pattern Saver" to save the output data.

    I set the "Output Data length" as 1048576 and it seems it always save 1048576…

  • AD9680 minimum JESD204B lane line rate

    Hi,

    I am evaluating an AD9680 and have an inquiry regarding the minimum lane line rate.
    I had setup the device with 2 lanes, single converter and sample size (N') of 16. I then operate the sample clock at 300MSPS. The calculated sample rate is therefore…

  • DDC with ad9680 and ad9208 driver

    Hi Support

    I currently have a design with multiple ad9680 running at full bandwidth mode with 2 channels at 500 Msps.
    Output is ADC A samples / ADC B samples.

    Now to save FPGA some resources I need to use the on-chip facility to do the first decimation…

  • ACE unknow AD9680-LF500EBZ

    I want to use ACE to capture some data with AD9680-LF500EBZ and ADS7-V2.

    But, ACE seems unknow the AD9680-LF500EBZ like the picture show.

    I also try the VisualAnalog with the same ADC board and it works fine.

    I am sure I had installed the AD9680 plug…

  • RE: ad9680 spi2.1: AD9680 PLL UNLOCKED

    Hi All,

    I've cherry-picked the following commits into our 2019_R2 branch (https://github.com/PrecisionWave/linux/tree/2019_R2_PCW) to get the ad9680 working with the ad9208 driver:

    32af9cfdac0e iio: adc: ad9208: IIO_CHAN_INFO_SAMP_FREQ use chip de…

  • Seed value for PRBS sequence,AD9680

    Hi team

    AD9680 datasheet, page 85 gives default/seed value for PRBS sequence it supports. My question is whether this seed value is general value for any devices (adc/dac) or its a specific characterized value for AD9680?

    I don't see any mention of seed…

  • AD9680 (using ad9680-1000ebz) clock-divider phase

    Hi EZ,

    I am evaluating AD9680. I connect the same signal to both Channels, I sample at 1GSPS and the data comes spot on the same.

    However no matter what I select in 0x10C the data from ADC ChA vs ChB is never shifted by any clock delay. 

    I've tried 1 GHz…

  • AD9680-FMC-EBZ

    HI !  I have bought the board AD9680-FMC-EBZ , wo was followed the link:EVALUATING THE AD9680/AD9690/AD9234 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki]

    I find the formula REFCLK = lanelineRate/20.  which I  wonder if it is REFCLK = lanelineRate/20?