• RE: AD9675 start code

    Hi, I have the AD9671's problem, when I set 0x188 to 0 ,the output is not zero , but when I set to 01 , the output is zero ,no matter how I config the register sequence of the AD9671 , I used software Tx_Trig , and ground the pin ,please help me ! this…

  • trouble shooting AD9675 JESD204B data read zero for intermittent

    1.Main IC: XC7A100T(FPGA) + AD9675
    2.Refclk: buffer IC drive the same 125MHz clock to both ADC & FPGA(GTP refclk)
        clock in 125MHz
        enable RF decimator

    4.Parameter setting is same with the IP core.

  • AD9675 migration from AD9671

              We are working to redesign an ultra sound scanner. It is found that the existing system uses the AFE AD9671 which we intend to replace it with AD9675. Here are my queries.
    1. Can the AFE AD9671 replaced by AD9675 without any hardware or software…
  • difference between ad9671 and ad9675

    Good morning

    I would like to know the difference between ad9671 and ad9675.

    They have both the same Tx/ Tx synthesis/ Rx bandwidth.

    They also have exactly the same EVM curve (for Tx and Rx)

    However the price difference is 80$ !

    The only difference I found…

  • RE: AD9675 programming and JESD204B lane rate

    The standard seems straightforward but it looks like there's a fair amount of firmware development involved. Just curious, I know there are other manufacturers would probably gain from such an effort on your part. <a href="">apkdodo.com/..…

  • AD9675 GPO polarity

    When I write to the GPO register in the AD9675 (0x00E), I get the inverse of what I expect on the GPO pins (though I'm reading them indirectly through a connected FPGA). Each GPO has a 100 K pull-up attached to 1.8V. The register description in the data…

  • Troubleshooting AD9675 JESD204B link

    The troubleshooting continues on our AD9675 design. We are unable to train/sync the JESD204B link. When we physically probe the SERDOUT± pins, we find they are static at 900 mV (common-mode voltage). We've checked that CLK± is running at 100 MHz and verified…

  • AD9675 data sheet typo? (ILAS repeat count)

    In the AD9675 data sheet Rev. A, Table 31 (Memory Map Registers), p. 54, register JTX_LINK_CTRL4 (0x145) has one field that sets the ILAS repeat count:

    Initial lane alignment sequence repeat count

    0000 0000 = 4 × K + 1 (default)

    0000 0001 = 4 × K …

  • AD9675 Frames per Multiframe (K) discrepancy in default value

    The AD9675 data sheet Rev A, p. 32 states "the K value is set to 32 by default in Register 0x152" but on p. 55 the default value in the register table corresponds to K = 16. Which is correct?

  • extract memory map register tables


    I was wondering, specifically for the AD9675 IC, are the memory map register tables stored somewhere in a format that one can use it in software? A csv or other format so one can incorporate it as an API in their software stack would make it convenient…