这个链接里面写了需要AD9671-EBZ，但是我到处找都没找到这一块评估板，请问到底有这块板子么？

AD9671 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design [Analog Devices Wiki]

Hi,

I didn't found  any instructions for AD9671 PLL N dividers setting ，I just can see the settings value in the SPI register table，but I don't know the principle，would you please send me some information? or can I just leave this parameter as its…

Hello,

I want to operate the following reference designs.

AD9671 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design [Analog Devices Wiki] 

Because I wanted to customize the source code, the source file was downloaded.

The jesd204B0_rx4…

Hello,

I'm looking for the schematic of following AD9671-EBZ.

I want to check the evaluation board.

Best Regards,

Mr.K

Hi all

I'm trying to interface my fpga (ultrascale+) to some AD9675 chipsets (so JESD204b devices). 

If I look at the example designs/projects, I get a bit confused, e.g. DAQ3 for zcu102 design:

1. If I'm correct I guess you could call the util_adxcvr…

Hello,

In the data sheet of the AD9671 Page 6 you find: Four-lane mode, JESD204B lane rates = 1.6 Gbps/2.6 Gbps/1.6 Gbps/2.5 Gbps.

If you choose Mode 3 with 80MSPS you get the results of two ADCs on one lane. With 8B/10B encoding the data rate should…

We have problems to synchronize the AD9671. It seems that the FPGA doesn't recognize the K28.5 characters. We clock the AD9671 with 100Mhz, so we should be in Mode 4. The RF decimator must be turned on, so the data rate is 50Mhz. The 8 ADCs of the device…

Good morning

I would like to know the difference between ad9671 and ad9675.

They have both the same Tx/ Tx synthesis/ Rx bandwidth.

They also have exactly the same EVM curve (for Tx and Rx)

However the price difference is 80$ !

The only difference I found…