• RE: AD9671/9675 to DMA

    hello,can you send FPGA code to me?  e-mail:w_kavin@126.com

  • How to configure AD9671 PLL N dividers ?

    Hi,

    I didn't found  any instructions for AD9671 PLL N dividers setting ,I just can see the settings value in the SPI register table,but I don't know the principle,would you please send me some information? or can I just leave this parameter as its…

  • RE: Does AD9671 really support 4 channel/lane mode?

    Hi, do yo solve it ? I have the same problem with you ,could you help me if you solved it?Thank you

  • AD9671 based on DAQ2 and DAQ3 reference design

    Hi all

    I first posted this question in high-speed ADC forum, yet was adviced to try here as well.

    I'm trying to interface my fpga (ultrascale+) to some AD9675 chipsets (so JESD204b devices). 

    If I look at the example designs/projects, I get a bit confused…

  • EVAL-AD9671, EVAL-AD9670 - Extraction of Raw Frequency Data from Analog Front End module and its recommended Data Capture Board module

    Hi Mr/Miss,

    Good day to you. I am planning to use either EVAL-AD9670 along with HSC-ADC-EVALCZ, or EVAL-AD9671 along with HSC-ADC-EVALEZ as a data acquisition system for underwater sonar applications. After reading the Visual Analog User Guide, I am aware that…

  • AD9675 migration from AD9671

    Hello,
              We are working to redesign an ultra sound scanner. It is found that the existing system uses the AFE AD9671 which we intend to replace it with AD9675. Here are my queries.
    1. Can the AFE AD9671 replaced by AD9675 without any hardware or software…
  • AD9671 with FPGA JESD204B IP has linked done,but the data is always 0 except 0x188 set to 0, but the data is not correct,why? please help me

    Hi, AD9671 with FPGA JESD204B IP has linked done,but  the  data is always 0 except 0x188 set  to 0, but the data is not correct, TX_Trig used software and the hardware is tie to zero ,SPI cofig sequence is follow the datasheet, L=2 , 80M sample clock , RF…

  • AD9671 with FPGA JESD204B IP has linked done,but sample data is always 0.

    AD9671 with FPGA JESD204B IP has linked done,but sample data is always 0.Then I set regsiter 0x11A to 0xFF to use test mode(sine wave).after setting,input data in FPGA is 0.there is no change.I don't know why.

  • difference between ad9671 and ad9675

    Good morning

    I would like to know the difference between ad9671 and ad9675.

    They have both the same Tx/ Tx synthesis/ Rx bandwidth.

    They also have exactly the same EVM curve (for Tx and Rx)

    However the price difference is 80$ !

    The only difference I found…

  • AD9671有评估板么?在参考设计中看到了,AD9671-EBZ

    这个链接里面写了需要AD9671-EBZ,但是我到处找都没找到这一块评估板,请问到底有这块板子么?

    AD9671 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design [Analog Devices Wiki]