• I am using AD9656 in my new project. I am wandering if there is an update application note for AD9656. I am looking for detail of AD9656 register application note, like AN-877.

    some register in appl note AN-877 doesn't exit in AD9656, and few register is updated in AD9656. Analog Devices needs to provide new application note for AD9656, not just point to an old appl note.

  • RE: AD9656 HDL?

    Hi,Dougl,Could you please send me this code as well?Thanks!my email is rake408@126.com

  • AD9656-EVAL

    Does the ADS7-V2EBZ support AD9656-EVAL?I found the DGP can't  recognize  the AD9656-EVAL,besides ,I tried to use the Visual Analog and SPI Controller Software,they all failed,the  FMC_12V doesn't appear,So ,does ADS7-V2EBZ really support AD9656-EVAL…

  • ad9656

    I run the program on the board designed by myself, using jesd204ip under Xilinx vivado, and external connection

    Ad9656 chip, using fast setting register to 0x44, sending custom data 12345678, can make sync up,

    but One of the channels is found to have…

  • AD9656

    Hi there,I meet problems about AD9656 recently. User Input Test Mode of ADC is OK,so i think JESD204 port works,but when it comes to normal mode ,no valid data come out from JESD port. I've tested the voltage Vref and Vcm and found that they are both…

  • AD9656/SPIController Inconsistencies

    Hello. I have a question about the programming of the AD9656 and some inconsistencies I see between the SPIController software and the datasheet. We are working on custom PCBs, so I am using SPIController just to produce a script file that I can use to…

  • AD9656 dynamic level


    We are using AD9656 evaluation board and we carry out the following test.

    We configure the ADC register correctly with 2,8Vpp input span, quick configuration : One ADC per lane etc.

    We put a sinus signal of 1MHz on the input A and check the digital…

  • AD9656 Evaluation

    Does the EVAL-AD9656 with the FMC connector interface with the Xilinx ZC706 Evaluation Kit?

  • PN23 testmode in AD9656


    I am using the 16bit-AD9656 in an FPGA project. I am able to receive data from the ADC, but would like to validate the 6Gbps link using the PN23 PRBS testmode. My VHDL PRBS-checker has been validated using real ADC-samples in another FPGA project…

  • AD9656 SDIO Level clarification


    Could you confirm me the following information :

    SDIO in input mode (SDI) : VILmax = 0,8V / VIHmin = 1,2V and VIHmax = 3,5V (if SVDD=3,3V)

    SDIO in output mode (SDO) : VOLmax = 50mV / VOHtyp = 1,78V => Why this level is at 1,8V whereas the power voltage…