• HDL for AD9656


    I'm working on ZCU102 with AD9656. can I please have have HDL.

    Also Anyone tried with ZCU102 or any recommended board.

    Thanks in advance


  • RE: AD9656 HDL?

    Hi Kavin,

    I've requested that sample FPGA source code written for AD9656 capture on the HSC-ADC-EVALEZ be sent to you.


  • PN23 testmode in AD9656


    I am using the 16bit-AD9656 in an FPGA project. I am able to receive data from the ADC, but would like to validate the 6Gbps link using the PN23 PRBS testmode. My VHDL PRBS-checker has been validated using real ADC-samples in another FPGA project…

  • RE: ad9656

    I have compared the hardware design to the reference design, there are no differents.

    I mearsure the devclk/sysref to ADC and FPGA, the clock is right.

    Now I configure AD9656 to ML=42, 100MHz sample clock, line rate = 4Gbps, and I connect 2 AD9656 to the…

  • RE: How to config AD9656 ?

    I experienced the same problem。Sometimes FPGA can received K28.5 and ILAS, but sometimes FPGA can't, and FPGA transceiver encouter the "8b/10b not in table" errors, and cause the link is down.

    And how do you solver the problem?

  • AD9656/SPIController Inconsistencies

    Hello. I have a question about the programming of the AD9656 and some inconsistencies I see between the SPIController software and the datasheet. We are working on custom PCBs, so I am using SPIController just to produce a script file that I can use to…

  • EVAL-AD9656 with ZCU102

    I am trying to connect the EVAL-AD9656 to a zcu102 board and I cannot find the FMC pinout and IO standards documented anywhere. Do you know where I can find this information so I can create an .xdc for the fpga? 

  • AD9656是否支持50MS/s - 125MS/s 范围内任意采样率?

    AD9656的产品手册上提到其采样率支持50MS/s至125MS/s不同挡位,因为我的项目原因,需要输入外部采样时钟,并且采样时钟是在60MHz - 120MHz间变化的的。

    我的问题是:AD9656是否支持在50MS/s - 125MS/s间的任意采样率?例如非整数采样率:61.44MS/s、122.88MS/s,等等。


  • RE: AD9656 dynamic level

    Hi Dougl,

    We have resolved our problem with the AD9656 AD Evaluation Board. In fact, we have changed the AD9656 of the board because the internal reference voltage was damaged because the serigraphy of board contained an error.

    Now, we don't understand…

  • AD9656 SDIO Level clarification


    Could you confirm me the following information :

    SDIO in input mode (SDI) : VILmax = 0,8V / VIHmin = 1,2V and VIHmax = 3,5V (if SVDD=3,3V)

    SDIO in output mode (SDO) : VOLmax = 50mV / VOHtyp = 1,78V => Why this level is at 1,8V whereas the power voltage…