thank you very much for your clear result
For a past project I used an AD9230 evaluation board with the HSC-ADC-EVALC interface board.
Now I'm moving to a 2-channel design and I was thinking to use the AD9655.
Is is possible to use it with the same interface board?
Since I needed external…
Can you tell us the max and min value in Vp for Vinx+ or Vinx- and a common mode value with Vref = 1,4V for AD9655 because it is not clear in the datasheet?
Also, do you have a newer datasheet (more recent that Rev. 0)?
Thank you in advance.
I want to evaluate the performance of AD9655 with its EVB. AD9655 is 16-bit ADC. But I find most of RF signal generators from Keysight or R&S are 14-bit or less. Could these RF signal generators be used as analog input signal generation for…
Currently, we have interfaced a single chip ADC AD9655 to an FPGA Multi Gigabit Transceiver RX lane (with quad deserializer pair and one ref clk) and we obtain good result.
A question is how to synchronize multiple chip AD9655 in order to use MGT…
I’m trying to determine the non linearity of the ADC AD9655 with the “histogram” method. Although the achieved results are in the range of the data sheet descriptions, something looks wrong. Instead of a straight DNL trend, I got a "sine wave"…
Presently I'm developing a data acquisition using AD9655 ADC. I'm using AD9517-4 for ADC clock. I'm planning to use kintex-7, KC705 evaluation kit for interfacing. Please give some reference VHDL code.
2. I'm also planning for a 16…
I have some question on determining the IF sampling capability of ADC's :
I've checked the ADCs selection table for ADC > 10MSPS
I would just like to know if the source code for the mentioned Eval and ADC board combo is available. There is a list , ftp://ftp.analog.com/pub/HSSP_SW/fpga, but the particular ADC does not feature there. If it is not available can someone recommend an…