• RE: Using lower sampling clock for high speed ADC ?

    Hi Jiwon,

    Thank you for your interest in AD9653.

    Though the AD9653 would likely work at a sample rate of 5Msps - 10Msps, we cannot guarantee that it will work under all conditions at those sample rates. As a result, I cannot recommend a sample rate…

  • RE: AD9653 No OS Driver

    Hi Emrah,

    Are you looking for an analog driver/amplifier to driver the AD9653 inputs? What is meant by "No OS"?

    The ADA4930 is a good amplifier that matches well with the AD9653 inputs, but I want to be sure I understand your question.


  • RE: CMRR for differential input ADCs

    Hi Les,

    Thank you for your question and interest in AD9653. You are correct that we do not have CMRR data for AD9653. There is nothing to hide here. We just have not taken that data.

    I'll send you an email to discuss further.

    Thank you.


  • AD9653 CLK FCO DCO connection to FPGA

    Dear Sir/Madam,


    With the connection from AD9653 to FPGA(Spartan-6), what is the voltage of the bank should FCO+ FCO- DCO+ DCO- CLK+ CLK- of AD9653 be connected to?

    PS: For ANSI-644 mode, the D0A D1A D0B D1B D0C D1C D0D D1D are connected to the bank…

  • AD9653 Test Mode

    Dear Sir/Madam,

    I am using the AD9653 configured in Test Mode to output "alternating checkerboard".

    Register settings are default with the exception of:

    0xD => 04

    Input clock is 200MHz. In Test mode either alternating checkerboard or…

  • RE: When is the DCO of AD9653-125 stable

    Hi Ronald,

    Thank you for your interest in AD9653.

    From AD9653 power-up everything will be stable within the 375us wake-up time as specified in Table 6 of the datasheet. This will be worse-than-worst-case for your scenario of stopping the clock, and…

  • RE: High Speed ADC reference design needed

    Hello gentlemen,

    The AD9653 is a 16 bit version of the AD9253, if that might be of interest.


  • RE: how do I know if an ADC is suitable for IF sampling, i.e AD9653 or AD9655?

    - however, the AD9653 also has higher jitter, which means the SNR degradation due to jitter will also be higher for AD9653 compared to AD9655

    What is the effect of this jitter? What is the cause of the degraded SNR?

    • Does the amplitude decrease…
  • RE: How is dithering possible with ADC 9653?

    Hi DeeCee,

    Thanks for your questions related to the AD9653. Yes, as you have stated, the thermal noise of the ADC itself drives the outputs when no signal is applied. You can see this behavior in the input-referred-noise histograms in the AD9653 datasheet…

  • RE: AD芯片的soft reset和chip reset区别