• AD9653 design

    I am getting difficulties in AD9653 code. Can i get refernece code for AD9653?

  • AD9653

    Hi! 

    We are interested in the AD9653 converter. We understand that we need the pack AD9653 plus HSC-ADC-EVALCZ to evaluate the ADC, is that right? If so, how much it costs? and more important, it is included some VHDL code exmaple to control the AD9653?

  • AD9653 CLK+/CLK- 100MHz fundamental and harmonics on VIN+/-

    Dear Sir/Madam,

    The AD9653 in question has a 100MHz AC coupled LVPECL reference clock (CK+/CLK-) similar to Figure 64 in AD9653 Datasheet.

    The main difference is the PECL driver manufacturer and termination resistors (150R to GND).

    The IBIS and measured…

  • RE: REFERENCE DESIGN FOR AD9653BCPZ-125

    Hi,

    I am going to use AD9653.

    I downloaded the Design and Integration File from  the website :EVALUATING THE AD9653/AD9253/AD9633 ANALOG-TO-DIGITAL CONVERTERS [Analog Devices Wiki] 

    In the file I found the design is for AD9253 but in the…

  • RE: Crosstalk about AD9653

    Hi Chen,

    Thanks for using the AD9653 in your system.

    • You said that "The second picture is the input of AD9653 when AD9653 is not working." When you say "not working", does that mean that the AD9653 is powered down?
    • The AD9653…
  • eval-ad9653  wrong ad results using AD9653_FIFO5_FPGA_SourceCode with chipscope

    i evaluate the ad9653 with hsc-adc-evalcz fpga board + eval ad9653 board.

    when i using visual analog , the sample result is right, but when i use the ad9653-fifo5-fpga source code firmware with xilinx chipscope , the result is wrong.

    why ?

  • RE: Undersampling with AD9653

    Hi Orlando,

    Thank you for your interest in AD9653. The AD9653 has no problem converting signals at the frequencies you mention. Even though the datasheet does not mention much about undersampling, the datasheet shows performance up through fIN = 200MHz…

  • RE: ADC Evaluation Board FPGA Reference Design

    No, I mean AD9653 which has 4 analog input.

    I get the answer about ad9643 but I did not get the answer about ad9653.

    Thanks,

    Muhammet

  • RE: How to set J9 jumper for 1.8v I/O on HSC-ADC-EVALCZ FIFO501B?

    Hi Stinver,

    Thank you for evaluating the AD9653. The HSC-ADC-EVALC works fine with the AD9653 evaluation board, with J9 in the 2.5V position.

    Are you seeing problems with J9 in the 2.5V position?

    Thank you.

    Doug

  • AD9653 Channel D problem

    Hi,

    I am debugging AD9653 with Artix-7 FPGA and referenced the ADC_interface supplied by XAPP524.

    The input of the signal is a sine wave which is fed by a signal generator. The outputs of each channel are monitored with a ILA in Vivado after the signals…