when i look at the datasheet of ad9650 i understand that if we want to use lvds mode we should configure the device through its SPI. Is there any other method, if there is not, do you know if there is a ready VHDL module in order to configure ad9650 through…
Hi, I am wondering what is the current limit on the AIN inputs for the AD9650,
I am designing a high speed sampling system that has a +-10V peak pulse so I need dc coupled inputs.
I use AD9650 in my design, it is 105MHz, now I can read reg #001, I can also read and write other reg.
But I can not write reg #00B, any value write to it when read is 0x00, I can make sure my work on SPI is OK, Why?
Hi dear Analog!
For better input matching, I need the S parameter of the analog input of ad9650 ,can you help me?
I'm using the ADA4350 to drive the AD9650. The front-end circuit of AD9650 is shown below. The sample rate is 20MHz.
When I input a 100KHz sine wave to the ADA4350, The sample data is a stepped sine waves when ploted.
I have another PCB of AD9650…
Dear Sir or Madam
I'm writing to ask for some help because I couldn't find the power supply rejection specification from the datasheet of AD9650.
Thereby , I come here…
I have some questions about AD9650 for multi-chip sync.
What it means "A vaild SYNC causes the clock divider to reset to its initial state."?
How can reseting clock divider synchronize multiple ADCs?
As AD9650 can be configured through SPI so we just need to connect only SCLK, SDIO, CSB with the port. All other pins likeSYNC, OEB, PDWN, DCO, OR should be left floating then ? or they have to be connected to the ground?
I am using the AD9650.
In my board, the noise appears in the VIN± pin of the AD9650 when the analog to digital conversion starts.
The amplitude of the noise is about 200mVp-p.
The noise is a square wave, and the same cycle as the sampling clock…