• AD9649-80 analog input range

    Hello,

    I have 2 boards with AD9649-80 out of 5 same boards that the input analog range is smaller : 1.2 Vptp instead of 2 Vptp. I used a DC analog input to check this.

    I use  the 1V internal reference  and also measured the Vref pin which is  0.990 V.

    I use…

  • ISE project of AD9649 ref-design

    Hello support team,

    My customer will design interface and controll logic of FPGA for AD9648. We couldn't find Ref-Design for AD9648 in Analog Devices Wiki site. We knew it isn't supported in FPGA ref-design of ADI.

    Is that correct?
    Then we found…

  • Calculation for input noise of AD9649

    I have found a formula from AN835 about the relationship between SNR and equivalent input noise,

    ,

    about which I have two questions.

    1. does the Noise represent 'rms' value or 'p-p' value?

    2. why it would be divided by 2*sqrt2?

    For…

  • AD9649-80 DCO jitter

    Hi,

    I plan to use the digital clock out in divide by two mode, 150MHz input 75MHz output.

    How much jitter does the chip add to this signal compared to the jitter in ADC clock input?

  • AD9649-40 VCM output delay

    Hello.

    Dose VCM output of the AD9649 have a delay from AVDD Power-up?

    In datasheet of internal circuits of VCM output. I watch it but I don't know.

    Best regards

  • Problem with output of AD9649 Evaluation Board


    I have a AD9649 Evaluation Board and I have read through the user guide EVALUATING THE AD9266/AD9649/AD9629/AD9609 ANALOG-TO-DIGITAL CONVERTERS [Analog Devices Wiki] , I am trying to get the ADC 2 complement output by standalone mode (without the SPI…

  • AD9649, clock below 3 MHz

    What happens if the ADC is clocked below 3 MHz? Is 2 MHz okay?

  • AD9649 : problems with SPI configuration interface

    Hi,

    My application uses three AD9649s controlled by an Altera Cyclone IV FPGA.

    The three devices have separate interfaces to the FPGA for the parallel data buses, and a common SPI controller (with three chip-select outputs) for the configuration interfaces…

  • Outputs scaling of  AD9649 evaluation board

    I have an evaluation board EVAL-AD9649-80, with a driver AD8138. They are DC connected. Now I found a very strange phenomenon that the digital output data value is about 60% of the analog input voltage. It looks like there is a scaling during A to D conversion…

  • Regarding Max Standby time for AD9649

    Hi , 

    We would like to use AD9649 in low power , but at the wake up time is 350 us this doesn't suit out requirement so planning to use Standby time .

    1.Could you please let me know if there a about figure for Max standby time or any jitter data…