• RE: AD9644 - driving DC-coupled signle ended analong signal

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  • RE: interface to input common mode voltage of AD9644

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  • AD9644 evaluation kit documentation

    Hi,

    I've got AD9644 evaluation card with Altera based FIFO card (HSMC-ADC-EVALCZ (FIFO_GX)).

    1. The documentation of ADC board is missing one sheet of schematic (http://www.analog.com/static/imported-files/user_guides/UG-294.pdf page 18 is duplicate…

  • Erratic BOM in AD9644-155 evaluation board

    Hi

    We have two AD9644 evaluation boards

    AD9644-80

    SNO:081512A

    AD9644-155

    SNO: 102411A

    The AD9644-80 board is working OK.

    The AD9644-155 board clock oscillator Y502 was found to be oscillating at 26.7 MHz, not 80 MHz as expected.

    When digging…

  • DSYNC input to AD9644

    I'm  new to using the JESD204 ADC interface.  I cannot find any timing specifications relative to

    DSYNC+/- for the AD9644. I know that SYNC is synchronous to the clock, but does DSYNC+/-

    need to be synchronized to the AD9644 clock? 

  • Control bit of JESD204A in AD9644

    Hi,

      I found a parameter CS (Number of control bits per conversion sample) in JESD204. The Data sheet of AD9644 also shows that the setting of CS could be 0,1,2. But there is no detail description about  control bits. I want know which block will generate…

  • Single link mode output on AD9644

    In single link mode, (referred to as the third output mode) both converters are output on

    one link using two lanes and  only DSYNCA.  After conversion to 8b/10b and optional

    scrambling, are the MSBs (bit19) of both converters output first, followed by…

  • FIFO Board

    do you have the schematics and the code for the FIFO-GX Board? which comes with
    the AD9644 and AD9641 EVAL Board?

     

    I’ve attached the schematics for the FIFO-GX board and have included a link
    below for the data capture code for the AD9644…