• AD9643 test modes


    I'd like to ask expert's clarification on test modes of AD9643.

    The first question is about test mode 1111=ramp output. What is expected slope of the ramp? I see ADC readings linearly go down from most positive value to most negative…

  • AD9643

    Dear  Sir/Madam,

    I wonder how to use AD9634 to switch betwee 0-1V and -1V~1V, is there any solution for it.


  • AD9643 Test Mode

    Good morning,

    I am using the FMCOMMS1 and the zc702 eval board.

    What is the logic for the test mode patterns “0100”, alternating checkerboard?  I’m running the part in “parallel interleaved” mode.  I get the following patterns.

    A – channel A

    B – channel…

  • AD9643 Data Process Time


    1.      I have a AD9643 with HSC-EVAL C data capture board. On performing a time analysis based on number of samples. It is clear that 65536 samples take nearly 150 ms to be processed. Is there any thing I can do to improve the performance on speed…
  • AD9643 initialization problem

    Hi Sir,

    I have a question for AD9643 initialization issue.

    When I power on the AD9643 and it will load the default value as Table 14?

    It means I don't use the SPI to initailize the AD9643 first time and it could be worked as well?

  • ad9643 2.5v  drive


             调试ad9643, 使用FPGA配置 d9643,发现fpga的vcco接到了2.5v的电源上,ad9643  datasheeet上SPI总线的逻辑电平不能超过2.1V. 用FPGA 2.5v IO驱动AD9643是否可行?

  • Question about AD9643

    Hi All,

    I have two question about input configuration of the AD9643. Please take a look at the attached schematic.

    The upper schematic is shown in its demo board user guide. The transformaer (ETC1-1-13) connection is not correct.

    Am I correct?

    In addtion…

  • about AD9643 Ibis

    Hi,i sue speed2000 simulate the data and clk line between FPGA and AD9643, and it was found that there was an obvious overshoot of AD9643 output on the simulation figure: ,What's the reason for this?is ibis model problem

    The following figure shows…

  • four AD9643 sync


    I want 4 AD 9643 sync.    I'd like to use a 200 MHz clock, distribute(use ADCLK 944) to 4 AD9643.  input without clock divider, do I need to connect sync input pin?


  • AD9643 Data Mode

    Hi all,

    I was wondering if anybody would be able to advise me how the AD9643 data configuration mode is setup.  By data configuration I mean Parallel Interleaved or Channel Multiplexed LVDS mode.  I don't see any bits in Register at SPI address 0x14 to…