• AD9643: Streaming Mode

    Hello,

    I have a question about the streaming mode of AD9643.
    In AN-877 STREAMING section, indicated as follows.

    "Similarly, the starting address is continually and automatically incremented/decremented, according to the mode, with no chance to directly change…

  • AD9643: Data value of zero volts input in invert mode

    Hello,

    I have a question about the AD9643 data format from our customer.

    Q. What value returns while inputting zero volts to VIN when using invert mode?

     According to table 11 of the datasheet(rev.F), 0x2000 will return in normal mode.
    The table 11 indicates…

  • AD9643: Sampling delay between ADC0 and ADC1

    could you please advise the sampling delay between ADC0 and ADC1 - I was not
    able to find it in the datasheet

     

    I have had similar questions come up in the past and the design of the AD9643
    is to keep the sampling instant of the converters as close…

  • AD9643 Junction-to-case (top) thermal resistance


    DEARS

    Please tell me the "Junction-to-case (top) thermal resistance" information of AD9643.

    Thank you.

  • AD9522-4驱动7片AD9643

    请问,用AD9522-4驱动7片9643,驱动能力够吗?我们实际在用的过程中,同时驱动6片AD9643 是正常的,到7片的时候,每次都会有一路AD空采样出的数据畸形?

  • AD9643 test mode 1/0 toggle

    I am FAE in Japanese distributor.

    Our customer will use AD9643.

    Data sheet mentions Test mode(0x0D) =“1110” is 1/0 word toggle.

    AD9643 has the interleaved mode and multiplexed mode.

    Does Dn in the interleaved mode output as shown in Dn(A)…

  • Ask a question about LVDS signal layout design of AD9643

    Hi,

    AD9643 is a high speed ADC with LVDS (ANSI-644 levels) outputs, when doing the PCB layout design,is it necessary to make one of the LVDS output differential pair or all the differential pairs

    be the same length? Do you have any suggestions or user…

  • RE: AD9643

    duplicate entry

  • RE: AD9643

    PCB diff trace is 100ohm