could you please advise the sampling delay between ADC0 and ADC1 - I was not able to find it in the datasheet
I have had similar questions come up in the past and the design of the AD9643 is to keep the sampling instant of the converters as close…
Please tell me the "Junction-to-case (top) thermal resistance" information of AD9643.
I am FAE in Japanese distributor.
Our customer will use AD9643.
Data sheet mentions Test mode(0x0D) =“1110” is 1/0 word toggle.
AD9643 has the interleaved mode and multiplexed mode.
Does Dn in the interleaved mode output as shown in Dn(A)…
AD9643 is a high speed ADC with LVDS (ANSI-644 levels) outputs, when doing the PCB layout design,is it necessary to make one of the LVDS output differential pair or all the differential pairs
be the same length? Do you have any suggestions or user…
PCB diff trace is 100ohm
please see CHANNEL/CHIP SYNCHRONIZATION section in datasheet
the ibis models seem to be generated pretty conservatively. try using a scope probe on the eval board, it would be better.