I'm confused about the description of the PN9 sequence in the AD9635 datasheet.

The text says that the seed value is all ones, which, for a 9-bit register, equals to 0x1FF. When trying to generate the first 12 values for that generator, i'm getting…

Hi ADI,

We need an ADC setup to sample a single-ended IF signal. We are considering the AD9635 as the ADC with the recommended ADA4927 as driver and to perform the a single-ended to differential conversion.

The IF signal has beat frequencies down to 1…

Hi,

I am evaluating AD9635 thanks to AD9645-125EBZ + HSC-ADC-EVALCZ.

Test need is to inject a clock at a frequency of 12,5 MHz at J602 input (P601 is removed).

Using VisualAnalog software in FFT mode, I am not able to measure any signal when the input clock…

Hello,
I want to ad9635 in DC-coupled.
it's possible for this device ? have an example of input schematic to use ?
Thank you for your help

Réda

Hi,

which is time needed to have the AD9635 up and running after power supply has been applied?

I'm not sure I can consider the value indicated for the "Wake-Up Time (Power-Down)" stated in the datasheet.

thanks

Regards,

Alberto

I noticed that if I change the value of register 0x18 from 0x04 to 0x00, the input span of the AD9635 become 1Vpp.

Do I have to expect a change in SNR in this configuration?

Thanks

Regards

The clock for an AD9635 is from an FPGA PLL in LVDS. In this case, can I directly connect the PLL clock outputs to the clock inputs of AD9635 with capacitors and resistors without using a clock buffer such as AD951x in Fig 60 on page 22  of AD9635 data…

The clock for an AD9635 is from an FPGA PLL in LVDS. In this case, can I directly connect the PLL clock outputs to the clock inputs of AD9635 with capacitors and resistors without using a clock buffer such as AD951x in Fig 60 on page 22 of AD9635 data…

Hi

I'm looking for the technical documentation (schematics, layout, user guide, ETC) of the AD9635, Dual, 12 Bits, 80/125MSPS ADC.

Where can I find it?

Thanks

Alon