I set several test mode of AD9634, and get samples from FPGA as shown below.
I think the three mode(one/zero word toggle, alternating checkerboard, ramp output) are passed. But for PN9 test, there are two zero word. I'm confused. Can someone tell me…
I'm planning to clock AD9634 straight from an FPGA at LVDS18, does anyone see a problem in that? Datasheet mentions "If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock", but how…
Hello
Our customer uses AD9634 then ask internal reference drift pecification but describes its specification in the datasheet.
Datasheet describes about the drift spec of gain error and offset error.
I understand that these two speficiation (TYP) are…
Hi UBOTI,
To place the AD9634 in test mode using the user test patterns you need to write register 0x0D to either 0x08 or 0x88. When register 0x0D is written to 0x08 the test patterns written to 0x19 through 0x20 will be placed on the ADC digital outputs…
Hi, I am using AD9634.When I use the test mode and use ramp out, I observed some glitches. as shown in the first feagure.
then I use a oscilloscope to check the digital signals, I I observed that, the digital signal from the scope looks wierd. it is supposed…
Not sure why I am getting the below error from the example. Should not all the env variables be pre set? or is there another issue at hand?
I wanted to run a simple test with the board before jumping into a BPSK example.
Please let me know if things look…
Hi
I have designed and assembled an expansion board of the AD9634 250MSPS ADC to the Avnet Microzed Zynq-7020 FPGA evaluation kit, I have followed all recommendations on signal integrity and clocking requirements.
I am now looking for both HDL and linux…
Hi,
The information for the SDIO as an output was not included in the AD9634 data sheet unfortunately. The SDIO driver from the AD9634 is very similar to the SDIO driver on the AD9683. You can substitute the values from the AD9683 for the SDIO as an…
Hello, everyone!
I am unable to find seed value for PN9 sequence. ITU-T standard says, that it should be 0x1ff; AN_877 says 0x092. But none of this equals the code that I get from ADC.
Maybe someone can post the seed value and 3-5 first output words…
Hello
AD9634 datasheet Figure 55 uses AD9510 for clock driver of LVDS.
The differential input voltage spec of AD9634 is 0.3V ~ 3.6Vp-p.
The differential output voltage of AD9510 is 250mV~450mV.
Out customer asks if AD9510 does not meet input specification…
