AD9634 datasheet Figure 55 uses AD9510 for clock driver of LVDS.
The differential input voltage spec of AD9634 is 0.3V ~ 3.6Vp-p.
The differential output voltage of AD9510 is 250mV~450mV.
Out customer asks if AD9510 does not meet input specification…
I read AD9634 datasheet.
In Figure 55. Differential LVDS Sample Clock (Up to 625 MHz), AD9634 is recever and AD9511 driver.
AD9511 Differential Output Voltage 250mV - 450mV.
AD9634 Differential clock input 300mV - 3.6V.
When AD9511 output 250mV, would…
I have designed and assembled an expansion board of the AD9634 250MSPS ADC to the Avnet Microzed Zynq-7020 FPGA evaluation kit, I have followed all recommendations on signal integrity and clocking requirements.
I am now looking for both HDL and linux…
Thank you for your answer.
I will use ADA4940 with AD9634
AD9634 OUTPUT voltage of VCM is 0.9V
SO I need Vocm around 0.9V.
The AD9634 PN sequences are nuanced similar to the AD9643/AD9613. Please refer to the following thread for more information on handling the PN sequence for the AD9634: PN Sequence Info.
The information for the SDIO as an output was not included in the AD9634 data sheet unfortunately. The SDIO driver from the AD9634 is very similar to the SDIO driver on the AD9683. You can substitute the values from the AD9683 for the SDIO as an…
Can't I have a layout drawing of the part loaded face because I'd like to know where of a board a part is?
（There was only a wiring pattern layout in UG-386.）
I'm planning to clock AD9634 straight from an FPGA at LVDS18, does anyone see a problem in that? Datasheet mentions "If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock", but how…
I've attached a plot for you of the typical INL for the AD9634-250.
The offset error and gain error parameters in the data sheet are indeed values obtained from measured data during characterization of the AD9634.