The AD9633 is certainly different than the AD9218, but it does have its own VCM pin. This VCM is an output reference what is very close to 0.9V at no-load. This output is used to set the common mode voltage of whatever is driving the AD9633…
Actually, our clocks for ADC are from clock distributor, where the clocks come from and branch to each ADC device. Is it still ok without using SYNC to apply synchronization function for all ADC devices?
If AD9633 can automatically…
Because DCO timing will track with data from the same AD9633, I recommend that you use the DCO from each AD9633 to capture its own data.
If you are using adaptive techniques where the FPGA dynamically adjusts to find the optimum sampling point…
The input common mode range of the AD4930 is 0.8V-1.1V. The common mode voltage from the AD9633 is 0.9 which is within the range of the AD4930. The AD4930 can DC couple into the AD9633. Here is an example schematic:
Hello Liu Xiang,
I am sorry for the late response. I have some more details on the SYNC for AD9633. The AD9633 contains an input clock divider with the ability to divide the ENCODE input clock by integer values between 1 and 8 via Reg 0x0B. This feature…
I am looking for FPGA reference design for AD9633.
Thanks, AD9633 will run at 100Msps.
We bought an AD9633 80MSPS and make a PCB to do the measurement.
But we find out there are some codes will go wrong on some regular voltage with the 80MHz CLK.
(no error In 20 MHz or 40MHz CLK)
(We didn't use the SPI to change any default…
The 1-lane 1x Frame mode will not support full sample rate (125MSPS) for AD9633. Is it because of the maximum speed of one lane, the limitation is 1G?
Can i configure it at 100Msps@10-bit with 1-lane 1x frame mode (It means the LVDS output…
Here is a discussion about using the FMC interposer with the AD9633, which is the 12bit version of the AD9653 https://ez.analog.com/fpga/f/q-a/84486/interfacing-ad9633-eval-board-with-ml605-using-an-adi-working-reference-design/84700#84700 . The…