• RE: AD9361 Custom Gain Table - cat: write error: File too large

    Loading the gain tables separately is not working for me? 

    Look at my custom gain table file above called: RX_Gain_Table_Flat.txt

    Is there anything wrong with it? If so what is wrong?

    If I split up these eight gain tables into 8 files and load them it does…

  • ADRV9364-Z7020 SOM

    Hello dear support team 

    From my customer:

    We are using the ADRV9364-Z7020ADRV9364-Z7020 SOM component for a GPS application,

    during development we encounter a strange phenomenon in RF modulation:

    When modulating RF with a constant value, and expecting…

  • AD9361 VDD_GPO Operating Range

    Hello,

    I'm trying to figure out what the operating range is for the AD9631 VDD_GPO supply. A question has been asked previously in 2014 (link below) and the response seemed to confirm operation at 1.8V.

    https://ez.analog.com/fpga/f/q-a/84625/ad9361…

  • RE: AD8054 settling time data

    Thanks for your answe.

    Surly it AD8045. Anyway, if I understand your answer- The Hi-Speed amplifiers, which specified  to 0.1%, is not converge to 0.01% because some physical properties, like DI ? or am I wrong?

    I found some "old" part, as the AD8036,…

  • Do I need calibration circuit for AD9744 to produce high-precision output?

    Hi,

    I want to build a high precision arbitrary waveform generator using ad9744 and ad5683r. As agilent 33220A used ad9744, so I am planning to build my circuit using 33220a and ad9744 official references.

    However, I found that there is a circuit in…

  • 图解软件定义无线电技术的革命性产品——射频捷变收发器AD9361

    图解软件定义无线电技术的革命性产品——射频捷变收发器AD9361 by ADIForum

    让我们通信基础设施部门的应用工程师Patrick Wiers给大家图解下射频捷变收发器AD9361能给通信应用以及您的设计带来哪些设计优势。



    RE: 图解软件定义无线电技术的革命性产品——射频捷变收发器AD9361 by ADIForum:

    大幅缩短产品上市时间,并简化设计、降低功耗,减少占用面积

    这是因为AD9631 不只是SDR,这款单芯片软件可配置收发器…

  • Parallel-to-serial converter to interface AD9361 CTRL_OUT outputs to FPGA

    Hi,

    I'm doing initial analysis and planning for designing a custom RF board with two AD9361 chips to interface with my FPGA board. The FPGA board that I want to use is the MYIR Z-turn board. The board uses Zynq-7020 SoC as a core device and has two…

  • RE: ad9363,fdd mode ,rx always can not get the right sample data

    I have do some test on the AD9631 demo board ,we can get the right data from rx port .but on ourself board , we always get the wrong data like constellation rotates.

  • RE: AD9361 projects can not Launching with SDK

    Please don't open multiple threads regarding the same issue. The discussion will be continued here: ad9631 projects "no source avaiable for "_start()" 

    Thanks,

    Dragos