• RE: CVT-ADC-FMC-INTPZB FMC Adapter Board and AD9629

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  • RE: AD9629 cannot output correct digital code at standalone mode

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  • 关于AD9629或者AD9268等的使用配置问题。

    AD9629或者AD9268等的使用配置问题。器件的非SPI功能模式下是不是给定AD时钟就能从AD输出端口读取数据?

    我是这样做的:1、FPGA产生50M时钟接至clk+,clk-直接GND;

                              2、FPGA的IO端口控制让CSB引脚拉高,SCLK和SDIO引脚拉低;

                              3、外围电路按照ADI的评估板原理图设计。

    我的差分输入VIN+为0.6V,VIN-为0.4V。但为什么器件输出时钟是全1?

  • AD9629-20EBZ BOM list

    Hello ,

    Our customer wants to get the bill of matelials list of AD9629-20EBZ.

    I have checked the wiki site for AD9629 evaluation board and I traced the link for bill of materials, but I could not find the list.

    Could you tell me the url to get the…

  • RE: How to interface my AD9629-40EZ with the ADSP-BF526 EZ-KIT?

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  • AD9629 in single ended mode. input minus vref.

    Hello,

    I ve got a question regarding the high speed AD9629 for a new design, in single ended mode. I need to know if my solution is correct. In single ended mode such as figure 39 of the datasheet. Can I use VREF to substract my input and shift down…

  • AD9629: nonlinear and missing codes in convert output

    Hi all,

    I used reference circuit of AD9629 (also CN0272) to make a PCB. When I use stm32 to get the convert results, I get the following two strange figures.

    Vertical ordinate is voltage. Horizontal ordinate is time. The green triangle curve is obtained…

  • AD9629 Vref question

    Hello EZ,

    Very quick question: I am looking at using the AD9629-20 in an application, and I am trying to determine if a voltage follower is required for fast current response on the VREF input of the AD9629-20.

    My external reference circuit consists…

  • AD9629 Single ended

    Dear all,

    I am reading the Datasheet of AD9629 Rev.0.

    There is one point that is not fully clear to me:

    why in the single ended configuration there is a 1Vpp signal instead of a 2Vpp (Fig.39 pag. 18) ?

    Does it mean that, in case of a DC value of Avdd…

  • 关于AD9629内部偏置电压和VCM的问题

    我使用的是AD9629_65,电路图如下,CSB,SCLK,PDWN,通过FPGA配置为1,1,0,选择内部偏置。

    现在不接输入和时钟,(之前接上时钟和输入,问题也一样。)VCM也悬空。用电压表测量VREF引脚电压是0.78V,理论值应该是精确的1.0V偏置,而VCM引脚电压是1.22V,输入引脚电压也有0.4V。RBIAS引脚电压0.57V的样子。

    这是用电压表测的数据,但是用示波器看,VREF和VCM引脚的信号是如下图所示,

    请问这是什么原因导致的,这是第二片AD了,之前换过一片…