• AD9628 sometimes stuck after power-up

    This is not really a question but an observation. I have tested several hundred of our own SDR boards featuring an AD9628 and a Xilinx Zynq SoC. The AD9628 AVDD and DRVDD supplies are powered by the same 1.8V rail as there are no limitations in the datasheet…

  • AD9628 A and B channel has different output

    These days we debug the ad9628 but we have two issues,as follows.

    we input the same Differential signal between A and B,when we samples,we not get the same data,the A channel data is smaller than B ten in binary.

    we tried to give the same dc signal,but…

  • AD9628 A and B channel has different output

    These days we debug the ad9628 but we have two issues,as follows.we input the same Differential signal between A and B,when we samples,we not get the same data,the A channel data is small than B ten in binary.

    we tried to give the same dc signal,but we…

  • AD9628 底噪问题

    你好,

    问一个ADC AD9628-125的问题,使用中发现,采样输出信号的底噪与输入信号功率关系密切,没有输入信号,噪底很干净,噪声水平与预期相当,使用19MHz -16dBm的单音输入测试,显示spur增加;而当输入功率增加到0dBm时,采样频谱的spur已经很严重,均匀、密集恶,而且spur level近似,采用10MHz或者2.5MLTE信号时,则显示输出噪底直接抬升,而与信号带宽无关,这种输出底噪随输入信号增加的问题,可能是哪里的原因?有哪些排查方向呢?

    附件是一个测试结果,显示低功率2…

  • Output Format AD9628

    Help on AD9628 needed.

    Hello Forum I am using an AD9628BCPZ-105 where both channels are needed.

    I configure the ADC channels both as 2-complement output data format, but i seems that only one channel is configured in this manner.

     SPISend2ADC(0x05
  • AD9628 register address 0x2E

    0x2E  Output  Open  Open  Open  Open  Open  Open  Open  0 = ADC A  ADC A = 0x00  Assigns an ADC to an

               assign                                                                             1 = ADC B  ADC B = 0x01   output channel

               (local)                                                                               (local)

    In the above register 0x2E it says that it is written to either or both channels (local) depending…

  • RE: AD9628 Freeze during initialize

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: AD9628 valid data window for FPGA

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • About AD9628 Input

    Hi,

    I would like to apply 0-2V input to AIN+ and AIN- in AD9628.

    Absolute maximum rating of AIN is 2 V when AVDD is 1.8 V.

    Is it possible to apply 2V to AIN+ and to apply 0V to AIN-?

    Best Regard,

    Yuya