• RE: AD9650 SYNC Input

    Hi Said,

    The AD9628 datasheet describes how to get the AD9628 synchronized. Please refer to Channel/Chip Synchronization section. The SYNC feature for the AD9650 and AD9628 work the same way. You will have to edge align the clocks to the AD9650 and AD9628…

  • RE: EVAL-AD9628

    Hi Sicfan,

    Thank you for your interest in AD9628.

    There are no DACs on the AD9628 evaluation board.

    The FPGA on the HSC-ADC-EVALCZ is programmed to capture data from the AD9628. The same FPGA is programmed differently for different ADCs.

    For AD9628…

  • AD9628: Power-up sequence


    I have some questions about the AD9628.

    Is there a power supply sequence between AVDD and DRVDD of the AD9628?

    Is there a sequence between CLK± inputs and release of PDWN?

    The output of ADC is unstable though I'm evaluating the AD9628.

  • AD9628 power on sequece

    Hi Engineer:

        Are there any design considerations about the sequence of DVDD and AVDD? In our design, the sequence is DVDD -> CLOCK -> AVDD, PDWN=0. However, AD9628 does't work. It seems that internal station is error. When I set PDWN=1 and…


    Hi Michael:

    I'm working with Pietro's group on this project - unfortunately the project that you sent (AD9628_FIFO5) doesn't seem to be for the ADC eval board in question (the AD9628-125EBZ).

    The AD9628_FIFO5 project uses LVDS differential…

  • RE: AD9628 Freeze during initialize


    Please refer to https://ez.analog.com/message/142761#142761 for AD9628 power-up recommendations.

    Best Regards,

    Tony M

  • RE: About AD9628 Input

    Hi Yuya-san,

    Applying 2V to AIN+ and 0V to AIN- will not damage the part, but this input amplitude is well outside of the full-scale conversion range of the AD9628.

    Full scale for the AD9628 is 2Vpp differential. This means that each single-ended side…

  • AD9628 register address 0x2E

    0x2E  Output  Open  Open  Open  Open  Open  Open  Open  0 = ADC A  ADC A = 0x00  Assigns an ADC to an

               assign                                                                             1 = ADC B  ADC B = 0x01   output channel

               (local)                                                                               (local)

    In the above register 0x2E it says that it is written to either or both channels (local) depending…

  • RE: Output Format AD9628

    Hi Doug,

    unfortunately there is no possibility to read from the Device.

    but with the command-sequence below there are proper results as expected (twos complement).

    SPISend2ADC(0x05,0x01); /*Device Index (global)*/
    Pause(200); /*Pause*/
  • AD9628 底噪问题


    问一个ADC AD9628-125的问题,使用中发现,采样输出信号的底噪与输入信号功率关系密切,没有输入信号,噪底很干净,噪声水平与预期相当,使用19MHz -16dBm的单音输入测试,显示spur增加;而当输入功率增加到0dBm时,采样频谱的spur已经很严重,均匀、密集恶,而且spur level近似,采用10MHz或者2.5MLTE信号时,则显示输出噪底直接抬升,而与信号带宽无关,这种输出底噪随输入信号增加的问题,可能是哪里的原因?有哪些排查方向呢?