• AD9625 Translator

    I am looking at using a translator to connect to the AD9625 SPI interface. I only need the SDIO as bi-directional but I am intending putting the SCK & CS on the same device (perhaps even IRQ, FD, PWDN & RSTB). Originally I was considering your ADG3304…

  • AD9625 DDC

    Hello,

    After having be able to use AD9625 in full bandwidth mode, I'm now trying to make it works in DDC mode. But it doesn't seem to work.

    I have several questions. Here they are :

    1) When in DDC mode (High BW or Low BW), are others JESD lanes…

  • 关于ad9625

    1.我用的是ad9625datasheet上没有标明输出速率,那输出速率是否就等于采样速率

    2.如果想要将采样的输出结果先存到存储器中然后再做处理,哪需要的存储器的传输速率和输出速率有什么关系

    谢谢

  • Interleaved AD9625

    I read in the specification that the AD9625 is capable of 2.5Gsps and was wondering if it is feasible to interleave two of these devices to achieve 5.0 Gbps?

    Thx!

  • AD9625 Reset

    To perform a reset of AD9625 using SPI I write at 0x000 0x24

    Is it necessary to use transfer register to perform this reset ? (On which address range transfer register must be used ?)

    Regards,

    PS : In datasheet Rev B, a reset sequence is proposed but…

  • AD9625 DDC

    Hello, I'm trying to configure the AD9625 for DDC mode (Quick Config 0x91). I'm using it with a Xilinx JESD IP which is configured for 8 Lanes. Will I have to reconfigure the Xilinx IP to 1 lane? 

    Can I just change the Quick COnfig to 0x91, and…

  • About AD9625

    Hi

       When I use AD9625 design, encountered some problems. The sampling rate  1Gsps can work properly, but in 2.4Gsps when not working properly.It is showed that the IP core inside the FPGA can not be locked.Is this the problem of speed?Who can give me…

  • AD9625 DDC Synchronization

    I'm working on a project that needs to synchronize multiple AD9625-2.5 chips across multiple FPGAs. I plan on having one FPGA control two AD9625 chips. I will have eight FPGAs in the entire system for a total of 16 ADC chips in the entire system. Let…

  • AD9625 DDC

    Hi all,

    Please advice to me.

    In the datasheet 33 page ~ "DIGITAL DOWNCONVERTERS (DDC)" @ AD9625,

    I can not understand the calculation of the transition band.

    "HIGH BANDWIDTH DECIMATOR

    "The filter yields an effective bandwidth of 120…

  • AD9625-2.5EBZ即AD9625的开发板在使用时需要在前端加驱动电路或驱动放大器吗?

    在使用AD9625的开发板时,还需不需要在前端加驱动电路或者驱动放大器?还有有没有合适的抗混叠滤波器适合AD9625开发板的,可以推荐一下吗?