• RE: AD9625 HDL reference design for xilinx ZCU102 EVM

    Closing this thread due inactivity.

  • RE: Can i use 'AD9625' for 'ADS7-V2EBZ' ?

    AD9625 does not have any infrastructure for ADS7-v2EBZ

  • ad9625 & ads7-v2

    Hi i need some help

    I'm looking for a way to use AD9625 with ADS7-V2 board.

    when i check this working. it is same to compare AD9625 and AD9680 in the schemetic.

    FMC connector's pin all same so i think AD9625, maybe can use at ADS7

    when i using…

  • AD9625 DDC

    Hello, I'm trying to configure the AD9625 for DDC mode (Quick Config 0x91). I'm using it with a Xilinx JESD IP which is configured for 8 Lanes. Will I have to reconfigure the Xilinx IP to 1 lane? 

    Can I just change the Quick COnfig to 0x91, and…

  • RE: AD9625 DDC

    Hi IanB, i'm looking for solution similar to this post. since the discussion took place on a conference call, do you recall or know what the solution to this issue was?

  • AD9625-2.5EBZ board layout pdf

    Can anybody provide me with the board layout design in .pdf format? My version of Allegro Viewer is too old to open the "AD9625 Board Layout (RevB).brd" file, and I'm getting Trojan virus alerts from Cadence's download link for the latest…

  • AD9625 MOTIF matlab simulation

    Hello,

    I have been trying to use the model that simulates on matlab AD9625.Downloaded all relevant code and examples from : https://github.com/analogdevicesinc/MOTIF_MathWorks/tree/master and successfully run the Main example.

    In my case however a modulated…

  • AD9625 SPI Reset Protocal

    I read from register 0x06e in the AD9625 getting the value 10000111 as expected.

    I then wrote the number 00000111 to the register 0x06e. The I latched 0x01 into register 0x0ff. This is to move the value from the ghost register into 0x06e. I read from…

  • 急!请问AD9625如何打开时间戳同步功能？

    请问AD9625的寄存器需要如何设置才能打开时间戳的功能？

    按照数据手册我将寄存器0x072设置为0x8B,将0x08A设置为0x22.数据经过Xilinx FPGA的JESD204B IP核，但为什么我观察到控制位恒为0？

    还有就是AD9625如果要使用时间戳的功能，应该设置为Subclass1还是Subclass0的工作模式？Xilinx FPGA 的IP核有需要注意修改的地方吗？

  • RE: AD9625

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    …