• AD9625 Input to Output Latency


    I have a question about the latency of the AD9625.
    As a system, I need to consider the time between the signal input to the AD9625 and the time the data is obtained.
    Can you please tell me approximately how many clock cycles is the latency from AD9625…

  • How does the AD9625 timestamp sampled data?

    How does the AD9625 timestamp sampled data?

    The AD9625 can use the SYSREF± pins in either of 2 modes: LMFC alignment for JESD204B subclass 1 or as a timestamp mode to append a marker to a particular sample.

    The SYSREF± pins in the AD96…

  • AD9625 Threshold Registers

    Hello all,

    I was looking in the datasheet regarding how to program the fast detect bit and noticed that the threshold registers were specified to be 16-bit programmable with 0V-1.2V analog input mapped from 0 to 16,384, respectively:

    But looking at the…

  • ad9625 sysref in subclass0 on FMCADC3


    I need to run the ad9625 on my fmcadc3 (Rev-A) in subclass 0 mode with the "timestamp" bit added on to the output data. I have all of the lanes up in DATA mode and the analog data from the ADC is transferring properly, but the sysref bit is not…

  • How is the Over-Range flag indicator set on the AD9625?

    What logic is used to flag overrange?  Just clipping?  Is one sample reading code 2048 enough, or is there some quantity that’s needed? 

    For the over-range control bit that is embedded in the AD9625 output data stream, only one sample that is equal…

  • Can I take a >256K sample FFT with AD9625 using HSC-ADC-EVALEZ?

    Can I take a >256K sample FFT with AD9625 using HSC-ADC-EVALEZ?

    Yes, you can take an FFT with as many as 4M samples using the following instructions:


    Attached is the Deep FFT FPGA code that you need to load within Visual Analog in place of the standard…

  • RE: AD9625 resolution

    hi, can you please provide screenshot or raw data?

  • RE: AD9625-2.0 Clock Input

    Hi, if your sample rate you wish to use for the AD9625 is 1920MHz, you will need to use a clock chip like the HMC7044 to generate that clock. the AD9625 does not have an internal PLL to generate the sample clock. It only has an internal PLL to generate…


    please follow the instructions as explained in the wiki user guide

    AD-FMCADC2-EBZ FMC Board [Analog Devices Wiki]