What's the meaning of CTAT voltage, what's the relationship between CTAT voltage and temperature.
I am using AD9625, when I use 4 lanes 1GSPS, it is normal, however when I use 8 Lanes 2.4Gsps, FPGA shows that it could not lock.
Could you please help check above issue.
What is the full scale analog input required for AD9625 in EVAL-AD9625 at J301?
My design is four AD9625 chips working at 2.4GHz sampling frequency, the clock is provided by a HMC7044 chip. After sampling the data sent to the FPGA, AD9625 TX JESD204B protocol configuration for the 8 LANES, F = 1, K = 32, Scrambling. The FPGA…
Thanks for explaining the flash routine.
So far, we can pinpoint the error to the message related to the AD9625 not being recognized by the SPI routine.
Our board goes like:
ad9467 spi32766.0: Unrecognized CHIP_ID 0xFF
And a working…
1) The evaluation board for AD9625 does have support for 3.3V on DVDD_IO & SPI_DVDD_IO. The datasheet for AD9625 will only specify 2.4 to 2.6V for these domains. The 3.3V support may be added in the future, but will not be reflected in…
I have some questions with AD9625, We set the sample clock at 2.4GHz with AD9516 and ADCLK948, but the ad9625
cannot work correctly, the rx_sync and rx_tvalid go low always . we measure the swing of sample clock, it is 1100mv VPP at the source…
Yesterday, I answered some frequently asked questions on a new 2.0GSPS 12b ADC, AD9625, that was recently released.
As with many GHz ADCs, there are typical questions by system designers about the operation and performance of the ADC. Today, I have…
I have an AD9625 eval board. Part numbers below.
I need to know how to get the FPGA configuration files that go with the HSC-ADC-EVALEZ.
The AD9525 on the evaluation board is only meant for use as a clock signal to AD9625. You will not be able to use the SYNC_OUT feature for the SYSREF input to AD9625.