Hi,

I want to use AD9613 for my dual channel application. I have seen two flavors in ad9613 interleaved parallel lvds and channel multiplexed even/odd lvds. I want to understand

1. why now there are lvds output for high speed adc/dac?. I understand…

hi

iam using ad9613 in my design

in our design we have taken our CSB tied low,

when iam trying to configure the adc iam not able to get control on the ADC.

iam confuguring the adc with 16 bit address and folowed by data

is it the right way to configure…

I wonder why this happens to my ad9613.

The problem is that ADC can get first channel data correctly. The problem is that I cannot get the data from channel 2, even if I get the data without doing anything(means nothing goes into ADC),

the data noise…

Hi

I want to use AD9613 instead of AD9643，and change the HDL code of AD9643 to match AD9613. I have some problems about PN sequence in hdl_2016_R1.

1. in axi_ad9643_pnmon.v   

assign adc_pn_data_in_s = {adc_pn_data_in[13:0], ~adc_data[13], adc_data[12…

Dear Sir.

I am using the circuit for single ended to double ended outputs .

The outputs are fed into a AD9613 .

I apply a signal of 2V @ 1kHZ at the input , I get no outputs at the resistor R97,R102.

Please Advise.

Ephraim Oved

Hi,

I'm working on an FPGA code to interface AD9613 to xilinx Zynq (artix 7). I'm hoping to get some help on how to align data clock edge to the center of data eye. There is a xilinx 7 series IP called IDELAYE2 that design to correct the phase alignment…

Hi, I have a question about spi addresses which from ad9613.

When I see the other matlab coding for spiwrite, the soft reset and digital reset .

But when I see the ad9613 datasheet, the address 0x08 has no reset.

the data 3(bit1 + bit0) is reserved…

Hello

I'm driving the AD9613 analog inputs from the ADA4930 differential amplifier.

I've looked at figure 47 of AD9613. It seems there is some mistake, since the FB+ (without dot) should be connected to IN-, and FB- (with dot) should be connected…

hi , how to configuration the test mode to validation the communication from ADC to FPGA ? 

gave me some guidance pls.