I want to use AD9613 for my dual channel application. I have seen two flavors in ad9613 interleaved parallel lvds and channel multiplexed even/odd lvds. I want to understand
1. why now there are lvds output for high speed adc/dac?. I understand…
The EVAL-ADC-FMC-INT should work with the AD9613 evaluation board although it has not been tested to date. There is a logic translation on the interposer to translate between VADJ and 3.3V which is done via U201. This is what gets transmitted…
Could you please clarify your setup? The AD9613 evaluation board is intended for use with the HSC-ADC-EVALCZ capture board. The bin file that should be downloaded to the FPGA for the AD9613 is ad9643_evalcz_04302014_0528pm.bin.
HADV6 is another…
Hi, I have a question about spi addresses which from ad9613.
When I see the other matlab coding for spiwrite, the soft reset and digital reset .
But when I see the ad9613 datasheet, the address 0x08 has no reset.
the data 3(bit1 + bit0) is reserved…
Input 0.672VPP differential analog square wave to VIN+A/VIN-A of AD9613，but the voltage converted by AD9613 is 1.23VPP.
The SPI register configuration remains the default vaule.
What causes the voltage to be inaccurate?
we want to use ad9613 in our zero-IF receivers, frequency of input signal is 0~100MHz.
can AD9613 be used in the zero-IF receivers?
I got it now. The AD9613 is not the same as AD9643. I found that AD9613 generate 13 PN code，send 12 LSB.
I wonder why this happens to my ad9613.
The problem is that ADC can get first channel data correctly. The problem is that I cannot get the data from channel 2, even if I get the data without doing anything(means nothing goes into ADC),
the data noise…
I'm driving the AD9613 analog inputs from the ADA4930 differential amplifier.
I've looked at figure 47 of AD9613. It seems there is some mistake, since the FB+ (without dot) should be connected to IN-, and FB- (with dot) should be connected…
customer feedback some information as below :
1. I want to ask if the clock source of LVDS is affected by the ADC's rising and falling frequency.
What is the bandwidth of LVDS? Is there any restriction on my input clock frequency?
2. And if…