• RE: VisualAnalog pattern saver

    Hi Younsu,

    The attached file here is an example of enabling the trigger function for the HSC-ADC-EVALCZ but for a different ADC part, the AD9629. It should still guide you to how to enable this feature for the AD9272. The only step that may deviate is…

  • ad9649 Linux driver

    We plan to use an ad9649 to capture a clocked analog signal at ~10MHz. The source has a symetric clock signal and a single-ended analog signal in the 0..1V range.

    I noticed that this ADC family (there's a handful that uses the same register settings…

  • RE: 关于ADC前端输入范围的问题



    其共模输入电压的范围为0.5 到 1.3V, 所以想要保证输入范围达到要求,就必须满足其共模电压输入要求

  • Interfacing AD9201 with AD9761

    I am sampling an audio signal, and I need an A/D converter that will best interface with the AD9761 DAC.

    The AD9201 is said to be the dual receive companion A/D for the AD9761 but I don't need the dual matched DACs

    for this particular application…

  • RE: about AD9266_80EBZ

    Hi Xiaodxi,

    Yes, you can operate the AD9266 without SPI. If you power up the AD9266 evaluation board the part will come up in a functional mode even if you don't use SPI. Nevertheless, it would be a good idea to put the part into non-SPI mode if you…

  • RE: Schematics of Rev.A AD-ADC-FMC interposer

    Hi ysuzuki,

    The CVT-ADC-FMC-INTPZA is no longer in production and has been replaced by the CVT-ADC-FMC-INTPZB. The schematic and related docs for the  CVT-ADC-FMC-INTPZB are avail at http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html. The current…

  • Problem with output of AD9649 Evaluation Board

    I have a AD9649 Evaluation Board and I have read through the user guide EVALUATING THE AD9266/AD9649/AD9629/AD9609 ANALOG-TO-DIGITAL CONVERTERS [Analog Devices Wiki] , I am trying to get the ADC 2 complement output by standalone mode (without the SPI…

  • RE: High-speed TTL ADC

    Hi Lior,

    Thank you for considering an ADC from Analog Devices. None of the ADCs I am familiar with have TTL outputs. We have several converters with parallel CMOS outputs. In these cases the output levels (VOH, VOL) depend on the output driver power…

  • RE: 关于AD9266的时钟沿和数据的问题!!!!


    手册的第7页中描述的参数 tskew就是输出时钟DCO的上升沿与数据位的变化沿之间的差异,典型的是0.1ns,是不是就是帖子中所述的“但是输出的数据的沿和时钟的沿是对齐的”。