• AD9578 reference input

    I have repeated this question as a new post, rather than as a comment in my previous post.


    Referring to the development board, I want to modify the XO4,XO3 inputs for an  external differential clock. I have added the balun to the board, however I find…

  • More AD9578 questions

    Dear Steve,

    Thanks for the reply. I have some further questions:

    Crosstalk spurs.  I have noticed that the data sheet has no specification for crosstalk spurs when PLL1 and PLL2 are generating different frequencies. Also between outputs 1 and 2 when…

  • AD9578 Dither and Dither scale settings

    Would you teach me the usage of Dither and Dither scale setting in the actual situation?

    Can I use them to reduce the power of spurious ?

  • AD9578 Dev board problem

    I have now purchased the development board, and are having problems with the 49.152MHz crystal oscillator. It seems that this is not starting on power up. Enabling the reference output, and examining the waveform shows a random series of pulses and noise…

  • Reference SDK code with configuring AD9578 PLL

    Hi, Can any one help me out with reference SDK code with configuring AD9578 PLL or Configuration steps

  • AD9578 frequence calculation formula puzzle

    Dear  SteveBeccue and ADI technical experts,

               Sorry to trouble you.

              After we read the AD9578 datasheet, we got confuse with below description, if the analysis progress is wrong please kindly help to correct it.

    a. In Page 26. calculation formula…

  • Configuring AD9578 over SPI Interface

    We have a 48MHz crystal on XO1 and XO2, and we are trying to generate a 100Mhz LVDS clock on OUT3.  We write the AD9578 register with the following values:

    Register 0 00000000
    Register 1 000000000000
    Register 2 00305d
    Register 3 24040000
    Register 4 0410

  • AD9578  Dither and Dither Scale

    Dear Steve,

        I am trying to minimise spurii at offsets of up to 10kHz. I am using rational mode, and do not understand the explanation given for the Dither Scale setting. The explanation implies that this must be recalculated for every frequency programmed…

  • AD9578 phase adjust and re-sync

    Dear Sirs,

         The AD9578 has phase adjust bits in registers 7 and 9.   In some configurations of my application, I have both PLL1 and PLL2 on the same frequency, with the same reference. This is so that I can perform a cross correlation to average the uncorrelated…

  • AD9578 crystal parameters with external clock

    It appears possible to change the crystal oscillator parameters when using an external clock. This has a substantial effect on integer boundary spurs.

    In my application I use a 1:1 transformer to drive the XO1 and XO2 pins. The drive level at the transformer…