I have a question about AD9559 device.
I cannot find the formula to calculate the frequency clamp function in AD9559 datasheet.
Please let me know the formula and some information about the frequency clamp.
Thanks & Best regards,
I have a question about loop bandwidth of AD9559 device.
In datasheet, AD9559 supports 0.1hz to 2khz loop bandwidth.
The DPLL is working well in the default configuration (50hz loop bandwidth)
But when we set the loop bandwidth to 0.1hz, the…
I want to use software for evaluation board AD9559. But I can't start it in Win7 and WinXP.
关于 AD9559，客户有部分细节需要 ADI 确认：
1、请帮忙提供 25MHz(Single), 分别输出 50Mhz/125MHz/156.25MHz(LVDS), BW 为50HZ，对应的 phase noise 曲线
2、输入103.125MHz(Single),分别输出50MHz/125MHz/156.25MHz(LVDS), BW 为50HZ，对应的 phase noise 曲线
50MHZ(LVDS) --phase noise
支持0延时的模拟PLL器件有AD9520, AD9522, AD9523, AD9524, 等。支持固定延时的数字PLL器件有：AD9548, AD9547, AD9557, AD9558, AD9559, AD9554.
We have four solutions:
1. The AD9578
2. The AD9558, AD9559, and AD9554-1. This are DPLL based jitter cleaning PLLs but also work as synthesizers. You might consider these if you want to ultimately have your clocks locked to a reference…
The AD9554 does not support 3.3V CMOS on it's outputs, it is a 1.8V device. Table 8 of the datasheet lists the output driver swings for the different modes.
The AD9559 is a dual version of the AD9554 which supports 3.3V CMOS outputs. However…
Thanks a lot to answer my question.
I have follow your description step by step to program my EEPROM, but it seems not successful.
Here are something I want to confirm with you:
1, I then loaded into the software the second setup that uses a different…
I just want to start with clarifying the term "hitless" switching as there is some ambiguity in its use in industry. At Analog Devices, hitless switching was defined as the process of switching from a primary line card reference to a secondary…