• RE: AD9557 frequency displacement between different 10 MHz references

    HI,

    The minimum slew rate the AD9557 data sheet mentions as meaningful is 315 us/s.

    I do not know the settings you use, but the DPLL DPD most probably functions at 100kHz, which means a max phase offset at the DPD level of 1/2/100E3=5us.

    At a slew rate…

  • Questions about holdover test conditions in AD9557

    In order to obtain the results of HOLDOVER SPECIFICATIONS shown in Datasheet table 14., How long the AD9557 needs to operate normally?

  • RE: DCO level of AD9557

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    Thank you,
    …

  • Jitter at output of AD9557 with input of gapped clock (missing pulses) ?

    Hi,

     

    This is continuing from a previous question about gapped clocks on AD9557 (ad9557 and gapped clock? ), which was replied by .

     

    I am currently working on a clock recovery circuit that should output a phase locked clock. The circuit includes…

  • AD9557 issue - frequency output is different from expected

    Hello,
    I have run into an unexpected issue with AD9557 evaluation board. As you can see in the screenshot from the settings, I provide XOA sine wave input of 50 MHz, the reference clock frequency is 80 MHz, and I expect to get 80 MHz on the output as given…

    • attachments.zip

  • RE: Clock Generator with hitless switch-over. AD9557, AD9548, HMC7044

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    …

  • RE: EVAL-AD9557 for generating clock signal that matches varying input frequency?

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    …

  • ad9557 and gapped clock?

    Can I use AD9558 or AD9558 with gapped clock for asynchronous demapping SDH from OTN?

  • AD9557 Input-to-Output delay?

    I have a relatively slow clock (nominally 9.38MHz) with appreciable cycle-to-cycle jitter which needs to be removed.

    It is important, however, that the input-to-output delay (phase) be consistent across power-up/reset cycles.

    (i.e. if the delay at one…

  • ad9557 and gapped clock?

    Can I use AD9558 or AD9558 with gapped clock for asynchronous demapping SDH from OTN?