Hello. I want to use AD9554-1 for de-mapping OTN signal. So, does AD9554-1 support gapped clock?
The AD9554 does not support 3.3V CMOS on it's outputs, it is a 1.8V device. Table 8 of the datasheet lists the output driver swings for the different modes.
The AD9559 is a dual version of the AD9554 which supports 3.3V CMOS outputs. However…
Can AD9554 output four Channel synchronous differential clocks from one reference clock input (65MHz oscillator connected to REFA)?
my purpose is to generate four same clean and low jitter clocks from the same source clock input.
the Schematic is as…
how set the Base Freq and and FEC ration of the AD9554 use the Frequncey configigration wizard
I am trying to generate 4 channel output clock of 167.187 MHz using AD9554. With the evaluation software, my design just use Ref A clock for the…
I am trying to generate a clock of 308.5714 MHz using AD9554. With the evaluation software, the words are supposed to be loaded to registers of the board, as shown below,
When the "read all" button is pressed, there are errors. It seems…
Thanks a lot!
I got it. That is to say a 32-bit DFTW DDS such as AD9554 can generate better-linearity sweep than AD9556 with a 24-bit DFTW, I am right?
I am bringing up a setup with the AD9554 eval board using a referenceA with 125MHz and system clock of 25MHz but the GUI states my reference is not valid and the PLL is in freerun (see below). I did verify the Reference (single-ended) with…
支持0延时的模拟PLL器件有AD9520, AD9522, AD9523, AD9524, 等。支持固定延时的数字PLL器件有：AD9548, AD9547, AD9557, AD9558, AD9559, AD9554.