• AD9545 outputs not being enabled

    This is possibly a bit of a unique case, but I'm having trouble bringing up the outputs of the AD9545 on a custom board, running Linux on a Xilinx Zynq-7000 SoC, and utilising the clk-ad9545 driver from ADI.

    My kernel version is Xilinx's 2021.2 release…

  • AD9545 unable to lock 1pps all the time

    Hello,

           The current application scenario is that the refaa of ad9545 inputs 1PPS signal, the outputs of pll0 and PLL1 track 1PPS signal, and OCXO crystal oscillator is connected to M0 pin for clock compensation. OCXO's accuracy is 10 ppb.

          The…

  • AD9545 锁定1PPS参考异常问题

    你好,

           当前应用场景是AD9545的REFAA输入1PPS信号,PLL0及PLL1的输出均跟踪1pps信号,OCXO晶振接至M0 pin脚进行时钟补偿。

          当前遇到的问题是,时钟PLL0及PLL1的锁定状态不稳定,PLL0锁定不稳定的时候,读取0x3100寄存器的状态,值为0x2a,表示DPLL0的频率没有锁定,读取0x3006的REFAA的状态,为0x10,表示REFAA为有效。PLL1锁定不稳定的时候,读取0x3200寄存器的状态,值为0x2c,表示DPLL1的相位没有锁定,读取0x3006的REFAA的状态…

  • AD9545 1pps ref clock can't phase lock

    Hello,

             I’m hoping to get some help with an issue I’ve been having. I’m trying to get a synchronized 1PPS signal and 30.74MHz from the AD9545, AD9545's REF is from GPS's 1PPS, it works at Internal Zero Delay mode. AD9545's DPLL…

  • Avoiding feedback loops in AD9545/AD9546 system clock compensation

    I have a setup with a low-frequency (100 Hz) synchronization marker embedded in a high-frequency (10 MHz) clock reference locked to GPS. I would like to use the high-frequency reference for system clock compensation, in particular to measure skew using…

  • AD9545 IN:10MHz External OUT:122.88MHz

    I need a low phase noise 122.88MHz output by using 10MHz external input.

    Does EVAL-AD9545 support such Input/Output?

    Let me know  how to setup AD9545 ACE.

    10MHz,+3dBm SG signal connects to REFA_P(J300).REFA valid turns green.

    however, I don't know how…

  • AD9545 Linux Driver

    Hello,

    For a project we are to integrate the AD9545 with out platform, for which the hardware design has recently been reviewed. We need to configure the AD9545 via I2C in Linux environment and I see a clock driver for the AD9545 was created this year…

  • Some questions about the AD9545

    Hello, engineer, I am working on a project, hoping to generate any frequency through AD9545. I completed the following test corresponding to the CSO file on my PCB board. In the test, I wrote the register bits in the CSO file into AD9545 through STM32…

  • The EEPROM of the AD9545 fails to be loaded

    ISSUE: The EEPROM of the AD9545 fails to be loaded when it is powered on. The IIC waveform is captured and the value of the 00 register (chipType value, fixed as 0x05) is incorrectly read, causing the AD9545 to stop loading.

    the bin and *.cso generated…

  • AD9545 setup questions

    Hello

                  Some questions as below. 

    1. Below figure is captured from AD9545 datasheet. Which Mx pin function should be set for 1 PPS input?
    2. If OCXO is connected to REFBB, we can enable AuxDPLL compensation for DPLLx, AuxNCOx, and TDCs? All component…