• RE: AD9540 Users Manual

    There is no user guide for AD9540 Eval board. We suggests that the AD9956 user guide might be helpful as AD9540 is a derivative of AD9956.

    Link to AD9956 User guide:

    http://www.analog.com/static/imported-files/eval_boards/37266156101257AD9956_PCB_0…

  • AD9540 EVM

    Hi ADIer,

    I am playing with AD9540EVM, but the LVCO-4505 is obsoleted, I can not find the D/S.

    What is the frequency range of this VCO?

    Thanks!

    J.C.

  • about AD9540

    我想使用贵公司的AD5460产生一个时钟,我想的得到的频率范围是1~100MHz,频率分辨率为1Hz,可以吗?

  • RE: AD9540 EVAL not detected

    Hi Neil, I’m not able to open the link you attached “here”. Can you check It? Please

    Thanks

    Luca

    Da: neilw

    Inviato: lunedì 28 marzo 2016 22:13

    A: Biondi, Luca

    Oggetto: Re:  - AD9540 EVAL not detected

    EngineerZone <https://ez.analog.com/?et=watches…

  • RE: AD9540 evaluation software Rev. 1.0.0 Runtime error 13

    Hi sfarah,

    Where did you get the installation file?

    I would first uninstall the program and re download the version on our web page. Running the installer from the webpage will also give you the option to uninstall the current version that you have…

  • RE: AD9540 Eval Board Controlled with Matlab?

    Hi,

    I moved this discussion in the clock and timing community.

    Someone should be able to assist you here on AD9540 inquiries.

    Best Regards,

    Sitti

  • PLL Lock status

    Hi Experts,

        Follow snapshot is the pll lock status from AD9540, is it an analog pll lock signal. I am wondering if the PLL is in normal locked status.

    Regards,

    Jason

  • AD9540 Eval board communication error

    I have installed the AD9540 evaluation software and drivers on a 32-bit Windows XP system and can't seem to get a response from the output of the board.  This board has an onboard VCO clock, from which I also cannot measure a response (J16).  I have…

  • RE: ADCLK944/948 - low frequency clock input

    Hi Kyle,

    Appreciate if you can recommend on CLK distributer with CML outputs, and following requirements:

    Nubmer of Inputs: 1

    Number of outputs: 4

    low jitter and low skew performance.

    The input clock frequency  range: 1Hz - 100MHz with a rise time…

  • RE: DDS selection

    Hi,

    I just forgot one question/information.....

    At the moment we have selected AD9540, with external VCO (72-76MHz)......so these things made life harder as we need only one low jitter clock. Due to external VCO we need to have an extra Loop filter…