• AD9528 input reference clock changing to RefB.

    Hi,

    We were configuring the AD9528 with input Ref clock REFA  and VCXO .The configuration was successful. Now we want to change the input Ref clock to REFB instead of REFA, for this I have changed registers

    0x0108 from value 0x2a to 0x52

    0x010a from value…

  • RE: AD9528 Status Monitor PLL1

    Hi,

    I went today in the lab and I played with the AD9528 trying to replicate the behavior you outlined.

    I did not see it. Everything behaved as expected.  PDF

    See attached the document describing what I did. Please tell me what you did to trigger it.

    P…

  • AD9528 - Dual VCXO Option

    Hello Clock and Timing Experts,

    I need to support two VCXO frequencies using the AD9528. Since the PLL1 Input Receiver Control Register let me select single ended VCXO clock from either negative or positive VCXO_IN pins, I wonder if I can use this to multiplex…

  • ad9528 reference clock issue

    I am using a custom adrv9009 board and a custom zcu102 board. I was reading about the AD9528 and came across this " There are limitations with the default hardware configuration in the scenario where user-desired device frequencies are not related…

  • AD9528 PLL1 Feedback source

    Hello,

    What is the difference between N2 or VCXO Feedback inside PLL1 of AD9528? is there anything to know between these two options in term of performances?

    Thanks.

    Cyril.

  • AD9528 software tool for generating different clocks

    Hi,

    I want to use AD9528 clock generator for different clock output, But the problem is cant find  a simulation tool where i can simulate this before implementing and also I checked with the software that was available for AD9528 but i was not able to config…

  • AD9528输出频率不正确

    我想要跳过第一级锁相环,将一个10MOCXO直接输入到第二级锁相环,最终从OUT0,OUT1输出125MHz,OUT2,OUT3输出3.90625MHz。我现在按照图中红框内的方式启用了doubler,设置好了了分频系数,用频谱仪测得的实际输出频率为128.65MHz,仍然不是需要的125MHz,我不知道问题出在了哪里,希望得到您的帮助,非常感谢!

  • AD9528中VCXO输出波形要求

    请问一下,如果AD9528中VCXO_IN信号不是方波,而是正弦波,会对输出信号频率造成影响吗?

  • RE: The loop bandwidth of PLL1 of AD9528

    Hi GChao:

        Set PLL1 charge pump current as 50uA and re-try the ADIsimCLK simulation.

  • AD9528 clock configuration changes for ADRV9029.

    Hi All,

    Can I change the input reference A (RefA) value to 30.72MHz instead of 122.88MHz?

    Previously REF A was 122.88 MHZ and now we want it to be 30.72 MHZ. We changed the same in 9029 TES and could see one difference in main.c file as show below

    So the…