• AD9528 PLL1 and PLL2 unlocked

    product = AD9528
    softwareversion =
    <detailed setup information>
    -- PLL1 --
     - Ref A -
        Input Freq: 32.0 MHz
        Ra: 4
        PFD Freq: 8.0 MHz…

  • AD9528/PCBZ Evaluation Board USB driver problem

    We have just bought an AD9528/PCBZ Evaluation Board. I have followed the instructions from https://wiki.analog.com/resources/eval/ad9528-user-guide#pc_connections, but the board is not recognised by my Windows 7 PC.

    After connecting the wall power supply…

  • AD9528 CLK input

    I want to drive CLK inputs of the ADRV9026 by using AD9528.

    SYSREF JESD204 and baseband clocks will be drived by outputs of the AD9528.

    Therefore, I will supply a cyrstal CLK input to AD9528.

    Can I drive REFA and VCXO_IN inputs of the AD9528 with a clipped…

  • AD9528 VCXO Input

    AD9528 has a VCXO input described as PLL1 oscillator input.

    I want to use AD9528 for two reasons:

    1-) SYSREF JESD204B clock generation (internally)

    2-) Multiplexing baseband clock input that is applied to REFA pin

    (REFA input will be drived with 40MHz…

  • HMC7044 vs AD9528

    I am designing a module with AD9375 RF Transceiver. i need to provide reference clock of 122.88MHz<219fs jitter.
    I came across AD9528 & HMC7044 which might meet my requirements.I calculated the Timing jitter using ADI Sim CLK as shown below,

  • AD9528 baseband clock and JESD240B

    I want to divide a TCXO source by using REFA and OUT1, OUT2, OUT3, OUT4 of AD9528.

    But in the datasheet of the AD9528, there is no information about its frequency stability.

    Since frequency stability is important for me, I used TCXO which provides low…

  • using ad9528 without refA and refB


    I'm using the ad9528 of the ADRV9009-W/PCBZ evaluation board.

    I would like to use the AD9528 without RefA and RefB.

    is there any possibility to use ad9528 based on the VCXO 122.88 MHz, and complete the calibration manually?

  • RE: ADS9 use SD card boot error and the TES shows AD9528 PLL not locked.

    Because adi_ad9528_PllLockDebounce show error:ad9528 not locked.I don't know how to exclusive the following factors.

    1. How to check if Ref A clock provided?
    2. How to check if the VCXO signal present?
    3. How to check if PLL1 and PLL2 of AD9528 locked?
  • AD9375 and AD9528 Design Review Support

    Dear Support Team,

    We are using AD9375 and AD9528 in our design. We have interfaced 4 AD9375 chips with Xilinx Zynq US+MPSoC(XCZU11EG). 

    AD9375 IC 1 & 2: One Tx & One ORx channel  is used operating at 4.4GHz to 5GHz ; Tx IQ Rate: 245.76MSPS & ORx…

  • AD9528: Does PLL1 really need to be locked when PLL2 is in Locked State ?

    Hi Team ADI,

    I am working on AD9528 and I am giving reference from AD9545 to  AD9528 VCXO.  

    -> AD9545 PLLs are locked as expected

    -> AD9528 PLL2 is locked as expected but PLL1 is not locked because of N1 divider. If I make N1 = 8 then PLL1 gets lock…