• QEC issue when bypassing ad9528 PLL1

    Hi,

    I'm having an issue with the adrv9008-1/W-PCBZ and adrv9008-2/W-PCBZ when bypassing ad9528 PLL1.

    My setup is composed from a zcu102 board, connected to adrv9008-2/W-PCBZ on HPC0 and adrv9008-1/W-PCBZ on HPC1. Tx1 is connected to Rx1 via an SMA…

  • RE: Clock configuration error when changing default ADRV9009 profile - ad9528 setting problem

    Hi  ,

    it is true that currently the ad9528 configuration from the profile is ignored and explicit values are hardwired in no-OS code.

    If you'd like settings from talise_config_ad9528.h to be used, please manually replace those hardwired values…

  • PLL LOOP Filter components - AD9528

    1. I am using AD9528 to generate clocks for AD9375.

    2. Reference clock used is 10 MHz. Output Frequency of interest is 122.88 MHz(Device Clock) & 0.96 MHz (Sysref)

    3. I followed this approach from the following Link.

    https://ez.analog.com/wide-band…

  • AD9528 PLL Loop filter Components

    1. I am using AD9528 to generate clocks for AD9375.

    2. Reference clock used is 10 MHz. Output Frequency of interest is 122.88 MHz(Device Clock) & 0.96 MHz (Sysref)

    3. I followed this approach from the following Link.

    https://ez.analog.com/wide-band…

  • ad9528 frequency offset

    hello, I am using a custom adrv9009 with a custom zcu102 board. we have used a VCXO of 122.88MHz with a frequency stability of 50ppm. when I try to receive a signal on the RX path of my custom adrv9009 there is an offset in the received frequency. I am…

  • AD9528 PLL2 配置

    您好!我想跳过AD9528的第一级锁相环,通过外接一个10M的OCXO直接输入到第二级锁相环,最终输出125MHz和3.90625MHz的时钟频率,但是我们设置好分频系数之后,用频谱仪测得实际频率为137.65MHz和4.3MHz,正好是我们需要频率的额1.1倍,我们不清楚问题出现在哪里,希望得到您的帮助!

  • AD9528 input reference clock changing to RefB.

    Hi,

    We were configuring the AD9528 with input Ref clock REFA  and VCXO .The configuration was successful. Now we want to change the input Ref clock to REFB instead of REFA, for this I have changed registers

    0x0108 from value 0x2a to 0x52

    0x010a from value…

  • RE: AD9528 Status Monitor PLL1

    Hi,

    I went today in the lab and I played with the AD9528 trying to replicate the behavior you outlined.

    I did not see it. Everything behaved as expected.  PDF

    See attached the document describing what I did. Please tell me what you did to trigger it.

    P…

  • ad9528 reference clock issue

    I am using a custom adrv9009 board and a custom zcu102 board. I was reading about the AD9528 and came across this " There are limitations with the default hardware configuration in the scenario where user-desired device frequencies are not related…

  • AD9528 - Dual VCXO Option

    Hello Clock and Timing Experts,

    I need to support two VCXO frequencies using the AD9528. Since the PLL1 Input Receiver Control Register let me select single ended VCXO clock from either negative or positive VCXO_IN pins, I wonder if I can use this to multiplex…