Hi, I want running a ADRV9008-1 + ZC706 in No-OS system.
So, I referred this page and created project successfully.
but, It show build error in "app_clocking.c" -…
My customer wants to use AD9528 as shown in the attached image.
When the customer tested the setting on the AD9528 EVB, the PLL2 of AD9528 was unlocked.
The customer replaced only the VCXO clock of EVB(122.88M) with the wanted frequency(156…
How can I simulate the filter parameters of the LF1 and LF2_CAP?
#ad9528#ad9371 When I power up the ad9528,I find the pin status0 and status1 are both 3.3V,but the datasheet of ad9528 has no reference about it.I tried to reset the ad9528,but it doesn't work.
No need to change any of the PLL2 settings.
Try the patch below.
diff --git a/arch/arm/boot/dts/adi-adrv9371.dtsi b/arch/arm/boot/dts/adi-adrv9371.dtsiindex e52264a..fdc5d0f 100644--- a/arch/arm/boot/dts/adi-adrv9371.dtsi+++ b/arch/arm/boot…
AD9528 is a separate chip and provide clock requirements on evaluation board. Evaluation board has a custom user space AD9528 driver implemented . The folder you have seen refer to same. Customer is free to choose AD9528 or some other clock chip.
Option 1 will be better. One AD9528 has 14 outputs. " The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals "
So for 8 Transceiver + FPGA you need only 2 AD9528. For second AD9528 you…
My customer want to use AD9528 as the following conditions(refer to the attched EVB setup file).
* AD9528 PLL1 setup : REF A:122.88MHz, PFD:30.72MHz, EXT VCXO:122.88MHz, Feedback source:VCXO input
* AD9528 PLL2 setup : PFD:7.68MHz, Internal VCO…