Greetings!
I would like to inquire if it is possible to achieve precise frequency control with EVALZ - AD9531-1? I'm interested in generating a clock signal that is a multiple of femtosecond laser output pulse rate, which can be something close to 80…
Q.
When a reference is switched from REFA to REFB in the AD9523/24/23-1 will there be glitch of the output clock signal?
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A.
The AD9523/24/-1 does…
I am working on a design with the AD9523-1 clock generator. In my design, there is:
an off board connector wired to the REFA input, which allows an external 10MHz reference signal to be fed into the chip;
an on board 10MHz TCXO, wired to the REFB input…
I am using the non-OS reference design of FMCOMMS1 on ML605.
I am very confused about the configuration on control registers and bit description of AD9523-1.
The "struct ad9523_platform_data ad9523_pdata_lpc" in AD9523_cfg.h
has the…
Hello everyone We have custom transceiver board and AD9523-1 is used to clock ADC,DAC, and PLL+VCO's. When we send clock signal to ADC there is a jitter problem in signal. We use crystek CVSS-950 Model 100 MHz VCXO and we run the AD9523-1 without giving…
Hello,
We are facing an issue in the SPI interface (read instruction) of the AD9523-1 clock generation chip. The SPI clock being generated by the controller is at 20KHz.
During a read operation, the data bit from the slave (i.e., AD9523-1) is supposed…
Hi,
Our customer used AD9523 before. But AD9523 NRND, they need to change to AD9523-1.
1. If they change to AD9523-1, do they need to modify the firmware or hardware?
2. AD9523-1 add VCO Divider M1 and M2 Coupling meanwhile add some register.
Could you share…
Again, more on an observation. In the ‘PLL1 Reference Clock Inputs’ on page 23 of the AD9523-1 datasheet (rev C), I am told to set bits 5 and 6 of register 0x01A to enable single ended mode. This disagrees with Table 40, which indicates that bits should…
I'm looking into using the AD9523-1 for clock distribution on a design I'm working on. I'm looking at the evaluation board gerbers, schematics, and the datasheet.
My application calls for a clock distribution board along the lines of the…
Hi All,
In my new design I'm using common reference clock for two AD9523-1 PLLs.
According to the datasheet of the device for Zero Delay Operation, the output clocks could be phase aligned with external reference.
In my case, I'd like to achieve…
