Dear Sir:

           I am using the AD9643 + HSC ADC_EVAL (FPGA). On this AD9643 EVB, it has AD9523-1 chip need to program.

  However, I found in the SPIController for the HSC ADC_EVAL, the .cfg file it provided is for AD9523, not for AD9523-1.

  I have checked…

I am using AD9523-1 in my design.  I am giving 125 MHz clock  to the  OSC_IN#  and 50MHz I/P to the REF A .

PD# = '1'

REF_SEL='0'

REF_Test='0'

EEPROM_SEL='0'

STATUS0/SP0='0'

STATUS0/SP1='0'

SYNC# = '1…

In AD9523-1 register 0x22C, bits 2 and 3 indicate the status of the two reference inputs. The bits are set when the corresponding input is 'OK'. But what does OK actually mean? That transitions have been detected on the reference input pin? That a clock…

I am working on a design with the AD9523-1 clock generator. In my design, there is:

an off board connector wired to the REFA input, which allows an external 10MHz reference signal to be fed into the chip;

an on board 10MHz TCXO, wired to the REFB input…

More of an observation than a question. In my AD9523-1 design, I am using REFA and REFB dividers set to 1. In the datasheet, table 42, it appears that I should set bits 0 and 1 of register 0x01C to bypass the reference dividers. If I do that, the device…

I am using a AD9523-1 and I am getting some jittering on the PLL1 output.

I have an AD9548 feeding 80Mhz to AD9523-1 which in feeds 10MHz to a number of other AD9523-1s. All the AD9523-1 seem to have this jitter.  I can make the issue worse by touching…

Again, more on an observation. In the ‘PLL1 Reference Clock Inputs’ on page 23 of the AD9523-1 datasheet (rev C), I am told to set bits 5 and 6 of register 0x01A to enable single ended mode. This disagrees with Table 40, which indicates that bits should…

Hello,

   We are facing an issue in the SPI interface (read instruction) of the AD9523-1 clock generation chip. The SPI clock being generated by the controller is at 20KHz.

During a read operation, the data bit from the slave (i.e., AD9523-1) is supposed…