I am using the AD9643 + HSC ADC_EVAL (FPGA). On this AD9643 EVB, it has AD9523-1 chip need to program.
However, I found in the SPIController for the HSC ADC_EVAL, the .cfg file it provided is for AD9523, not for AD9523-1.
I have checked…
For AD9643, AD9613, AD6649, or AD6643 Family Evaluation Board and HSC-ADC-EVALCZ, how to configure the Internal AD9523 to configure SPI controller to Generate 250MSPS Sample Rate
You can change the clock rate for the DAC via the I2C interface. But be aware that the clock is generated by AD9523-1 on the board. For an example on how to program the AD9523 take a look a the AD9523 No-OS driver.
We are using the AD9643 + HSC_ADC_EVALC, and we have tried to use the way you proposed to setup the AD9523. However, it didn't have any CLK output on the OUT2. After I checked the PLL chip on the AD9643 EVB, it is AD9523-1. And I have checked…
There is the AD9523 (VCO from 3.6 GHz to 4 GHz) and the AD9523-1 (VCO 2.94 GHz to 3.1 GHz). These are two different chips. The DAQ2 board features the AD9523-1. So the supported VCO range is from 2.94 GHz to 3.1 GHz.
Is there a particular procedure to verify and make sure AD9523-1 is successfully locked?
I am using the reference design and no-OS, it seems that AD9523-1 is not locked
as AD9548 OUT1P/OUT1N and AD9523-1 OUT5 are of similar frequency but not phase…
I am using AD9523-1 in my design. I am giving 125 MHz clock to the OSC_IN# and 50MHz I/P to the REF A .
PD# = '1'
SYNC# = '1…
I should have looked a bit closer, it does seem to change later in the function (outside of ad9523_setup) looks like it is this function.
fmcomms1/AD9523/AD9523.c:int64_t ad9523_out_altvoltage6_DAC_DCO_CLK_frequency(int64_t Hz)
Our most direct alternative to the LMK04800 series is the AD9523 and AD9523-1.Unfortunately, we don't cover that range of VCO frequencies any better than they do.
Those are AD9523 settings. Take a look here: https://github.com/analogdevicesinc/no-OS/blob/master/fmcomms1/AD9523/AD9523_cfg.h