• AD9517-3 Clock distribution

    Hi,

    Iam using AD9517-3 Clock distribution to generate the LVPECL 1GHz, but we are not able to lock that device &  also no responce from the device,

    in ideal condition, at charge pump waht is the voltages levels at CP pin, after locking what is the…

  • AD9517-3 occasionally loosing lock

    Hi,

    I'm using AD9517-3 clock synthesiser with the internal VCO mode for clock synthesis for data converters.

    1. The synthesiser fails to lock occasionally while attempting to reconfigure.

    Is there any sequence to be followed other than that mentioned…

  • PFD operating frequency (AD9517-3)

    Hello!

    We are going to use AD9517-3 with its 2 GHz integrated VCO to generate 400 MHz clock for some ADC circuit. The reference clock for the PLL will come from a low-noise 50 MHz source. What phase detector frequency should be selected to achive lowest…

  • AD9517-3 on-chip VCO

    Hello,

    We are using AD9517-3 on-chip VCO working at 2048MHz with a 10MHz reference.

    Following the ADIsimCLK ("Frecuency Tune Dialog") the VCO tuning voltage

    should be around 1.375. But we get 1.68 in some boards and 1.29 in others

    In this…

  • AD9517-3 usage on 4DSP FMC110

    Hello - has anybody used this setup and can help with configuration?  I am trying to configure the AD9517-3 such that the LVPECL outputs are at 250MHz.   The input ref on the FMC110 per their spec is 100MHz.  I am unable to get the PLL to lock.     I am setting…

  • Clock Input Level of AD9517-3

    Hello,

    I am designing clock circuit using the AD9517-3.

    I have two questions about CLK INPUTS.

    Pls refer to P.6 Table3.

    1.Data sheet describes "Input Level differential is 2Vp-p(Max).

    Pls teach me the maximam input level of case of Single…

  • AD9517-3 Calibration complete and cannot lock

    Hello, 

    we use ad9517-3  to generate 100MHz clock, we only use OUT0 OUT1;

    the REF is 10MHz,

    R = 1

    when readback the register 0x01F, it is 0x4E;

    the below is configuration data:

    0 : dout <= 'h000099; // enable sdo;
    1 : dout <= 'h001800; // VCO cal…

  • Using the AD9517-3 tuned to 2.0GHz

    Hi All,

    I would like to use the AD9517-3 with a 10MHz input clock, tune the VCO to 2.0GHz and drive the LVPECL outputs at 2.0GHz.

    I realize that the datasheet limits the LVPECL to 1.6GHz when the output is created from the VCO.  However, is this som…

  • AD9517-3中VCO的问题 ????

    目前在看AD9517-3的手册中,有几点不理解,希望同事们帮忙解答一下,谢谢啊??

    1 :如果使用内部VCO与PLL的模式,那么内部VCO的频率范围怎么保证呢 ? 是用过硬件来保证在1.75G-2.25G吗 ??

    2 :在公式Fvco = Fref/R * (P*B +A )中的Fvco 是指的out输出频率吗 ?? 还是指vco的输出频率?? 这个VCO的频率和1.75G-2.25G中的频率有什么关系呢?

    3 : 如果是指VCO的输出频率,那么是不是还要经过几级分频器才能输出呢 ??

  • 关于AD9517-3的VCO的疑问?

    关于AD9517-3的VCO的疑问?

    AD9517-3的片上VCO的频率范围是1.75GHz-2.25GHz,但manual的Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies中,却可以通过10MHz参考时钟配置出小于100MHz的VCO频率,请问这怎么和 VCO的频率范围是1.75GHz-2.25GHz不冲突?能在片上产生出小于100MHz的VCO频率吗?