Hi, My name is Haichuan LIN.

     I have already read about the AD9517-3 data sheet. And there is

no information whether AD9517-3 clock input accepts sine wave.

In data sheet, AD9517-3 clock input accept 150mVpp(1V/ns is prefered).

Here, I want to make…

您好，

我们在使用AD9517-3的过程中发现OUT0 OUT1没有时钟信号输出，只输出一个大概2V的高电平，OUT2 OUT3有时钟信号输出，OUT0/OUT1OUT2/OUT3的输出频率都是设置为120MHz，LVPECL输出电压设置为780mV（默认值），使用交流耦合。请问是怎么回事？

OUT4 OUT5 OUT6 OUT7都有时钟信号输出。

Hello,

     For a new project we are using the AD9517-3. Prior to this we have successfully programmed and used the AD9523-1.

The problem right now is that there is no response from the AD9517-3 in a 4 wire interface.

The steps we follow are as follows…

Hi,

Just confirmation, AMR of voltage from RESET to GND on AD9517-3 is same as SYNCb (-0.3 to Vs+0.3)?

In the datasheet, there is no description of AMR for RESET pin.

Thanks,

TM

您好，我们想得到120MHz的时钟信号，请问为什么ad9517-3不能够锁定，参数设置如下：

R = 1    A=0x04    B=0x16

Prescaler P,use DM mode (Divide-by-8 (8/9 mode))

VCO divider = 3

Channel Divider=0x21（分频系数为5）

参考时钟为10MHz，PFD为10MHz，使用内部VCO

请问是什么原因？

多谢！

用AD9517-3 输出50M频率，其中输入参考频率10M，并且是稳定的恒温晶振，但是幅度会有+-50mv的波动，控制AD9517-3后，读取0X001F寄存器提示PLL已经锁定，VCO也已经校准完成，但是此时用示波器测试AD9517-3的输出，发现输出频率在50MHZ+-0.2MHZ 波动，请问这是正常现象吗？

如果不是，能够给个建议来解决这个问题??

thank you

Hello,

         The problem is that the PLL is not locked and the output freq is not correct.

We have a 200MHz differential reference in and the loop filter is same as that on the eval board.

Reset is pulled high and Ref_Sel is tied low.

After writing all…

Dear Sir/Madam,

AD9517-3 on-chip VCO frequency range is 1.75GHz-2.25GHz, but the manual's Table 28. showoing using a 10 MHz Reference Input to Generate Different VCO frequency  less than 100MHz, is this conflict with teh  VCO's frequency range 1.75GHz…

hello guys.

I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.

The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The…

Hi,

Iam using AD9517-3 Clock distribution to generate the LVPECL 1GHz, but we are not able to lock that device &  also no responce from the device,

in ideal condition, at charge pump waht is the voltages levels at CP pin, after locking what is the…