• AD9517-3


    我们在使用AD9517-3的过程中发现OUT0 OUT1没有时钟信号输出,只输出一个大概2V的高电平,OUT2 OUT3有时钟信号输出,OUT0/OUT1OUT2/OUT3的输出频率都是设置为120MHz,LVPECL输出电压设置为780mV(默认值),使用交流耦合。请问是怎么回事?

    OUT4 OUT5 OUT6 OUT7都有时钟信号输出。

  • AD9517-3

    Dear Sir/Madam,

    AD9517-3 on-chip VCO frequency range is 1.75GHz-2.25GHz, but the manual's Table 28. showoing using a 10 MHz Reference Input to Generate Different VCO frequency  less than 100MHz, is this conflict with teh  VCO's frequency range 1.75GHz…

  • AD9517-3 Clock Input

    Hi, My name is Haichuan LIN.

         I have already read about the AD9517-3 data sheet. And there is

    no information whether AD9517-3 clock input accepts sine wave.

    In data sheet, AD9517-3 clock input accept 150mVpp(1V/ns is prefered).

    Here, I want to make…

  • AD9517-3 AMR of RESET


    Just confirmation, AMR of voltage from RESET to GND on AD9517-3 is same as SYNCb (-0.3 to Vs+0.3)?

    In the datasheet, there is no description of AMR for RESET pin.



  • AD9517-3 SPI Interface


         For a new project we are using the AD9517-3. Prior to this we have successfully programmed and used the AD9523-1.

    The problem right now is that there is no response from the AD9517-3 in a 4 wire interface.

    The steps we follow are as follows…

  • AD9517-3 Clock distribution


    Iam using AD9517-3 Clock distribution to generate the LVPECL 1GHz, but we are not able to lock that device &  also no responce from the device,

    in ideal condition, at charge pump waht is the voltages levels at CP pin, after locking what is the…

  • AD9517-3 lock issue


             The problem is that the PLL is not locked and the output freq is not correct.

    We have a 200MHz differential reference in and the loop filter is same as that on the eval board.

    Reset is pulled high and Ref_Sel is tied low.

    After writing all…

  • AD9517-3 on-chip VCO


    We are using AD9517-3 on-chip VCO working at 2048MHz with a 10MHz reference.

    Following the ADIsimCLK ("Frecuency Tune Dialog") the VCO tuning voltage

    should be around 1.375. But we get 1.68 in some boards and 1.29 in others

    In this…

  • How to config the AD9517-3 registers(fine delay ) to produced 180-degrees LVDS Outputs?

    hello guys.

    I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.

    The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The…

  • Clock Input Level of AD9517-3


    I am designing clock circuit using the AD9517-3.

    I have two questions about CLK INPUTS.

    Pls refer to P.6 Table3.

    1.Data sheet describes "Input Level differential is 2Vp-p(Max).

    Pls teach me the maximam input level of case of Single…