• Synchronizing multiple AD9517-1

    I am using the AD9517 on two boards, and i am trying to synchronize all outputs such that the phase/timing between outputs on both board are repeatable at every power-up or reset cycle.

    I have made all the necessary provisions:

    1. External 10MHz reference…

  • AD9517-3 Clock Input

    Hi, My name is Haichuan LIN.

         I have already read about the AD9517-3 data sheet. And there is

    no information whether AD9517-3 clock input accepts sine wave.

    In data sheet, AD9517-3 clock input accept 150mVpp(1V/ns is prefered).

    Here, I want to make…

  • AD9517-1 Clock input Impedance

    Do you have impedance vs frequency data on the AD9517-1 clock input?

    The whole input range would be useful,  but ~1.12GHz in particular.

    Any additional information would be greatly appreciated.

  • AD9517-1 frequency range conflict

    The data sheets are a little conflicting. I would like to use this part to drive an AD9739 via the ADCLK914 at 2.4GHz. I would also like to generate a 1.2GHz LVDS/analog clock to a national ADC12D1800. The AD9517 would generate the clocks from a 10MHz…

  • AD9517 Internal VCO

    Hello,

    I am moving away from my ZedBoard with the AD9467 FMC card and towards my custom board. I just got the board up and running and am attempting to change my source code to make the AD9517 use the internal VCO instead of the external oscillator that…

  • How to config the AD9517-3 registers(fine delay ) to produced 180-degrees LVDS Outputs?

    hello guys.

    I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.

    The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The…

  • AD9517-1 delay to output of channel divider

    Q 

    AD9517-1 delay to output of channel divider: When I look at figure 57 "SYNC
    Timing When VCO Divider Is Used—CLK or VCO Is Input"(datasheet rev D) (that is
    how we are using our design now), it takes 14 to 15 cycles at the channel…

  • 如何将AD9517-1的输出时钟相位固定？

    我需要将一个80MHz时钟作为参考，分出640MHz、160MHz以及80MHz三种频率的时钟。

    目前的做法是使用内部VCO和PLL：

    VCO产生2560MHz的信号，N分频64倍到鉴相器

    VCO分频器倍数设定为4

    分频器0设置by pass，输出640MHz；

    分频器1分频4倍，输出160MHz；

    分频器2.1分频8倍，2.2是by pass，输出80MHz；

    分频器3.1分频8倍，3.2是by pass，输出80MHz；

    0x019寄存器中关于R、A、B计数器设置成SYNC信号同步或者异步reset…

  • AD9517-1 Ext Clock and Internal VCO Simlutaneously

    Can the AD9517-1 be configured to operate the internal VCO/PLL AND also accept an external clock for distribution, without connecting that external clock to the N-divider?

    It appears that the ext clock input is ONLY intended to be used with an external…

  • AD9517-1 False reference switchover in automatic mode.

    I am using the AD9517-1BCPZ in an automatic reference switchover mode and also to generate various frequencies. REF1 is a 10MHz signal from a Tektronix function generator (AFG310) but in the actual application it will be a GPS derived signal from a GPS…

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