Do you have impedance vs frequency data on the AD9517-1 clock input?
The whole input range would be useful, but ~1.12GHz in particular.
Any additional information would be greatly appreciated.
Do you have impedance vs frequency data on the AD9517-1 clock input?
The whole input range would be useful, but ~1.12GHz in particular.
Any additional information would be greatly appreciated.
I am using the AD9517 on two boards, and i am trying to synchronize all outputs such that the phase/timing between outputs on both board are repeatable at every power-up or reset cycle.
I have made all the necessary provisions:
1. External 10MHz reference…
Dear Kyle,
Thanks a lot for your prompt help, it's really appreciated.
I was able to apply the procedure you mentioned.
The USB connection is now ok.
I have configured the AD9517-1 and it works, I can observe the 1GHz on the out 2.
Problem solved…
The data sheets are a little conflicting. I would like to use this part to drive an AD9739 via the ADCLK914 at 2.4GHz. I would also like to generate a 1.2GHz LVDS/analog clock to a national ADC12D1800. The AD9517 would generate the clocks from a 10MHz…
Hi,
We’re having custom board base on AD-FMCJESDADC1-EBZ. Now we’re facing a problem with AD9517-1 which can’t generate output on any channel.
There’re three boards, the first one AD9517-1 can generated output as expected. The second…
Hi Paul
I am not saying that NXP has any errata sheet or any document relating to the AD9517-1.
What I ment to say was that if NXP had a issue with their processors they would release a errata sheet and mention a workaround. Note I am not finding fault…
Can the AD9517-1 be configured to operate the internal VCO/PLL AND also accept an external clock for distribution, without connecting that external clock to the N-divider?
It appears that the ext clock input is ONLY intended to be used with an external…
我需要将一个80MHz时钟作为参考,分出640MHz、160MHz以及80MHz三种频率的时钟。
目前的做法是使用内部VCO和PLL:
VCO产生2560MHz的信号,N分频64倍到鉴相器
VCO分频器倍数设定为4
分频器0设置by pass,输出640MHz;
分频器1分频4倍,输出160MHz;
分频器2.1分频8倍,2.2是by pass,输出80MHz;
分频器3.1分频8倍,3.2是by pass,输出80MHz;
0x019寄存器中关于R、A、B计数器设置成SYNC信号同步或者异步reset…
Hello,
I am facing a serious issue with the Lock Detect signal of the AD9517-1 device. I am not using Analog
Lock Detect or Current Source Lock Detect. Only the normal Digital Lock Detect (DLD).
The SPI communications work ok and I am getting the frequencies…