R = 1, PD = 8, A = 0, B = 3
The loop filter is the same schematic with AD9789EV.
Ref in-100MHz , OutCLK-2.4GHz
PLL Frequency locking is well.
Phase noise is fine.
But the frequency of 1~10KHz offset the shakes.
What is the problem?
Hi, My Job is Thermal Engineer. Flotherm user
AD9516-3 Thermal Datasheet : Theta JA (24℃/W)
I want to Theta JC and Theta JB (4-layer board in still air in accordance with EIA/JESD51-7)
I want to make DAC clock 500 MHz in AD9135-FMC-EBZ. The AD9135-FMC-EBZ has AD9516 clock generator.
The OUT1 of AD9516 is connected to the clock pin of AD9135 in schematics.
According to the document that the input clock of AD9516 is 250 MHz
the problem you have is outlined in the data sheet, page 46: "there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to asynchronous nature of SYSC signal with respect to the clock edges inside the AD9516"…
My customer has used AD9516-1 reference input in the following conditions.
- REFIN : Single-ended LVCMOS, AC-Coupled, 10MHz square wave
Recently, she found out the reference input conditions for 10MHz on the datasheet as below.
Does she have…
Hello, I have some questions about AD9516-3.
When using an external VCO, how the LF pin should be ? Should the LF pin be connected to VS, GND or others ?
And could you tell me other attention when using an external VCO ?
My customer is using AD9516-1 for his application.
By unknown reason, voltage at Ground and 3.3V power are increased to 0.5V and 3.8V respectively.
In this case, What could be happen to AD9516-1 ?
Will AD9516-1 not be affected from this power…
My customer is using AD9516 with the clock buffer of TI as shown below(refer to attached datasheet).
She said that if 10MHz input of clock buffer was connected directly to REFIN of AD9516, there was no problem and when she checked clock performance on…