• AD9515

    Hi, I want to use AD9515 as clock driver to AD9230. According to the spec of AD9515, the low level of clock output is 3.3-1.76=1.54V for LVPECL and 1.0V for LVDS. However, AD9230 recognizes clock as low only when the voltage is below 0.8V. I dont understand…

  • AD9515 Power requirements

    I will be using AD9515 as clock divider for a part that is 10MHz-1GHz synthesizer with LVPECL and LVDS up to 1GHz and LVCMOS up to 250MHz. How can I estimate the power requirement (max.current draw) for the AD9515?

  • AD9515 input

    Can anybody suggest a part that can convert 200mVp-p/100MHz Sinewave generated from OCXO to LVCMOS digital clock signal/100MHz? The output dutycycle should be 45-55% and jitter should be less than 50ps.

    Can I use AD9515 clock divider for this application…

  • AD9515 Slew Rate minimum Requirement

    i'm going to use AD9515 chip in my design for converting 100MHz signal to 10MHz signal
    Slew Rate calculation: for 100MHz 1 cycle time will be 10ns. So, if i divide it by 4 maximum peak voltage point can be obtained at 2.5ns.
    I'm providing the input…
  • RE: 关于高速AD差分时钟驱动的问题


  • using AD9515 for making coincident IO_UPDATE signals

    Hi everyone,

    I want to synchronize two AD9915 DDS according to AN-1254 document. In this document AD9515 is used for distributing IO_UPDATE to DDS ICs. It is indicated in the document, IO_UPDATE signals should be coincident for two DDS ICs at the last…

  • AD9515 Setup pin(S0-S10)equivalent circuit

    See datasheet Figure 28,the equivalent circuit Resistance is inside in AD9515? 

  • AD9515 Phase Start High

    Hi, could someone please explain the difference between "Phase" and "Phase (Start High)" options in Table 14 in the AD9515 Datasheet?

    Thank you.

  • Sinewave input to AD9515 and LVCMOS o/p

    Can I feed 200mVp-p Sinewave to AD9515 and get 45-55% dutycycle at LVCMOS o/p?

  • 怎样启动和停止AD9233采样