Hi, I want to use AD9515 as clock driver to AD9230. According to the spec of AD9515, the low level of clock output is 3.3-1.76=1.54V for LVPECL and 1.0V for LVDS. However, AD9230 recognizes clock as low only when the voltage is below 0.8V. I dont understand…
The AD9515 inputs are self biased as noted in Table 1 of the datasheet. Therefore you can AC couple an LVDS input as you are showing. Also, an LVDS signal meets the 150mVp-p sensitivity requirement of the AD9515 also listed in Table 1. Therefore a differential…
Can anybody suggest a part that can convert 200mVp-p/100MHz Sinewave generated from OCXO to LVCMOS digital clock signal/100MHz? The output dutycycle should be 45-55% and jitter should be less than 50ps.
Can I use AD9515 clock divider for this application…
I will be using AD9515 as clock divider for a part that is 10MHz-1GHz synthesizer with LVPECL and LVDS up to 1GHz and LVCMOS up to 250MHz. How can I estimate the power requirement (max.current draw) for the AD9515?
I want to synchronize two AD9915 DDS according to AN-1254 document. In this document AD9515 is used for distributing IO_UPDATE to DDS ICs. It is indicated in the document, IO_UPDATE signals should be coincident for two DDS ICs at the last…
See datasheet Figure 28,the equivalent circuit Resistance is inside in AD9515?
Hi, could someone please explain the difference between "Phase" and "Phase (Start High)" options in Table 14 in the AD9515 Datasheet?
Can I feed 200mVp-p Sinewave to AD9515 and get 45-55% dutycycle at LVCMOS o/p?
The AD9513, AD9515 and AD9525 were used for synchronizing multiple AD9915 as discussed in this application note. The evaluation boards for these parts are commercially available.