AD9634 datasheet Figure 55 uses AD9510 for clock driver of LVDS.
The differential input voltage spec of AD9634 is 0.3V ~ 3.6Vp-p.
The differential output voltage of AD9510 is 250mV~450mV.
Out customer asks if AD9510 does not meet input specification…
How do I configure the AD9510 register?
My company is designing acquistion board and we targeted AD9253 as its ADC. We will use FPGA to configure ADC and PLL and to retreive data from it. Due to the limit of available pins on our FPGA I want to minimize interfaces as much as possible…
How do I know which VCO will work best with the AD9510?
Yes I write in the register 0x5A after each instrution.
The outputs seem static or with low frequency, my frequency measurement says it goes from 250Mhz to around 6MHz for each channel.
The FUNCTION pin is being used for RESETB. Also I sometimes have…
I am not using the CLK1 input on the AD9510. Can I just leave it floating?