• AD9510: Evaluation PCB

    1 . Is the output for the external low pass filter a current or a voltage? 
    2. How is the maximum and minum voltage that can be presented in reference and
    CK2? 
    3. RcPSet in my case is 5.1 Kohm how can i change it?

     

    Question 1:
  • AD9510 Soft Sync Function

    Hello,

    We use an AD9510 to distribute a 150MHz clock applied to the 9510 CLK2 input.  The outputs must also run at 150MHz so each output's divider is placed in bypass mode.  We require that all the 9510 outputs operate in phase and it appears that…

  • AD9510 soft sync

    Hi,

    I'm having trouble with a 4DSP FMC108, 4adc at 250MHz implementation. It uses the AD9510 and I was having to much relative phase from the adc outputs. After I used softsync the relative phase became much lower. But sometimes the softsync doesnt…

  • AD9510 Register Configuration Reset

    Is there some way to hard reset the PLL counters without losing all register
    configurations?

     

    Register 0x09 has bits to hold the R and N dividers in reset. You can set and
    clear these to get different phases.
  • AD9510: Outputs not in Phase

    for evalution board AD9510, on the CLK1 input 1001.6 MHz, ratio 8 for output5
    and output6 equal 125.2 MHz. For on/off, on/off ext. clock (1001.6 MHz) have
    shift phase between output5 and output6 equal 90 or 180 or 270 or 0 degree.

     

  • AD9510 floating clock input

    I am not using the CLK1 input on the AD9510. Can I just leave it floating?

  • fractional frequency synthesis with AD9510

    hello Guys...

    Just to confirm, Can AD9510 Generation fractional frequency?

    How about the performance (phase noise and spurius) in this mode?

    My project is:

    ref in: 0.625 or 20 MHz

    output frequency 1: 117.5 MHz

    output frequency 2: 117.5 MHz+ dozens…

  • AD9510时钟配置问题

    请问哪位大神配置过AD9510,我现在想通过配置PLL输出一个1.6M的时钟,配了好几次都不成功,希望大家给指导一下,谢谢了!还有就是那个PLL参考输入REFIN是多少了?FormerMember

  • ad9510 vs ad9520 differential output jitter

    I'm currently using the 4 LVPECL outputs of an ad9510 to simultaneously clock 4 ADCs. It's a ratiometric measurement, so the most important clocking parameter is the differential jitter between the 4 channels. I don't think this characterstic is spec…

  • 请教关于AD9510的问题

        最近在调试的一个电路板A中使用了AD9510,调试过程中出现了一些问题,很是困惑,请教一下大家:

         按照设计,AD9510的OUT0、OUT1使用LVPECL输出,OUT2,OUT3不使用,OUT4、OUT5使用LVCMOS输出,OUT6、OUT7使用LVDS输出

    1.OUT2、OUT3无法关闭,即使在配置字中选择了Disable,仍然有输出,频率为CLK2的一半;并且OUT2的输出信号Vpp达到4V左右,OUT2B无输出,OUT3、OUT3B输出Vpp也达到4V左右,这些信号与LVCMOS类似…